• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.555-559
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• 2003

In this paper, a new CMOS RF model for RF IC design including the capacitance effect, the skin effect, and the proximity effect between metal lines on the Si surface is proposed for tile first time for accurately predicting the RF behavior of CMOS devices. The capacitances between metal lines on the Si surface are modeled with the layout. And the skin effect is modeled with a parallel branch added in equivalent circuit of metal line. The proximity effect is modeled by adding the mutual inductance between cross-coupled inductances in the ladder circuit representation. Compared to the BSIM 3v3. the proposed RF model shows good agreements with the measured data and shows well the frequency dependent behavior of devices in GHz ranges.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.30-33
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• 2015

In this paper, we proceeded a study on the Hybrid RF based development of the smart phone Application skin disease monitoring using CMOS camera. we proposed an image transfer technology which can use the CMOS camera and we developed the smart phone application which can be possible to use a remote monitoring for skin disease. Image transfer technology using Hybrid RF communication applied for WiFi using CMOS camera. We implemented the function which can use a remote monitoring using Wi-Fi. These suggestion can be a good example for endoscopic applications using hybrid RF based smart phone application of skin disease monitoring using CMOS camera.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.2
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• pp.304-309
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• 2019

This paper presents a CMOS RF-to-DC converter for video surveillance disposable IoT applications. It widely harvests RF energy of 3G/4G cellular low-band frequency range by employing a tunable impedance matching network. The proposed converter consists of the differential-drive cross-coupled rectifier and the matching network with a 4-bit capacitor array. The proposed converter is designed using 130-nm standard CMOS process. The designed energy harvester can rectify the RF signals from 700 MHz to 900 MHz. It has a peak RF-to-DC conversion efficiency of 72.25%, 64.97%, and 66.28% at 700 MHz, 800 MHz, and 900 MHz with a load resistance of 10kΩ, respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.3
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• pp.123-127
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• 2001

The prediction method of the parameter C/sub gs/ of CMOS transistor is proposed by calculating the mobil charge in inversion layer of COMS transistor. This parameter C/sub gs/ decided on the cutoff frequency in MOS transistor in RF range and coupled input and output. This parameter C/sub gs/ in RF range is very important parameter in small signal circuit model. This proposed method is contributed to developing software of extracting parameter value in equivalent circuit model. The method provide the important information to construct a RF nonlinear model for multifinger gate MOSFET. This method will be very valuable to develop a large signal MOSFET model for nonlinear RF IC design.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.421-422
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• 2008

In this paper, CMOS RF front-end circuits for an L1/L5 dual-band global positioning system (GPS)/Galileo receiver are designed in $0.13\;{\mu}m$ CMOS technology. The RF front-end circuits are composed of an RF single-to-differential low noise amplifier, an RF polyphase filter, two down-conversion mixers, two transimpedance amplifiers, a IF polyphase filter, four de-coupling capacitors. The CMOS RF front-end circuits provide gains of 43 dB and 44 dB, noise figures of 4 dB and 3 dB and consume 3.6 mW and 4.8 mW from 1.2 V supply voltage for L1 and L5, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.9-16
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• 2000

MOS transistors are fabricated and evaluated for RF IC applications such as mobile communication systems using 0.35m CMOS process. Characteristics of MOSFETs are analyzed at various channel length, width and bias conditions. From the analysis, cut-off frequency ($f_T$) is independent on channel width but maximum oscillation frequency ($f_{max}$) tends to derease as the channel width increases. As channel length increases, $f_T$ and fmax decrease. $f_T$ is 22GHz and fmax is 28GHz at its maximum value. High frequency noise performance is improved with larger channel width and smaller channel length at same bias conditions. NFmin at 2GHz is 0.45dB as a minimum value. From the evaluation, MOSFETs designed using 0.35m CMOS process demonstrated a full potential for the commercial RF ICs for mobile communication systems near 2GHz. And optimization methods of the CMOS transistors for RF applications are presented in this paper.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.251-256
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• 1999

RF CMOS 집적회로 기술은 CMOS 기술의 급격한 발전과 더불어 최근 크게 주목 받고 있다. 이는 CMOS가 제공 할 수 대량생산 능력으로 인해 기존 RF IC의 저가격화뿐 아니라 미래의 복합.다기능 무선 멀티미디어 단말기 구현을 위란 single chip solution을 제공 할 수 있는 가능성이 가장 높기 때문이다. 본 논문은 먼저 개인 휴대 통신 단말기 시장을 전망해보고, 향후 전개될 다양한 무선서비스에 대응하기 위한 RF CMOS 집적회로의 소자 및 설계 기술개발 현황과 향후의 발전 전망을 기술한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.68-73
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• 2009

This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

• ETRI Journal
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• v.21 no.4
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• pp.1-8
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• 1999

Thick metal 0.8${\mu}m$ CMOS technology on high resistivity substrate(RF CMOS technology) is demonstrated for the L-band RF IC applications, and we successfully implemented it to the monolithic 900 MHz and 1.9 GHz CMOS LNAs for the first time. To enhance the performance of the RF circuits, MOSFET layout was optimized for high frequency operation and inductor quality was improved by modifying the technology. The fabricated 1.9 GHz LNA shows a gain of 15.2 dB and a NF of 2.8 dB at DC consumption current of 15mA that is an excellent noise performance compared with the offchip matched 1.9 GHz CMOS LNAs. The 900 MHz LNA shows a high gain of 19 dB and NF of 3.2 dB despite of the performance degradation due to the integrating of a 26 nH inductor for input match. The proposed RF CMOS technology is a compatibel process for analog CMOS ICs, and the monolithic LNAs employing the technology show a good and uniform RF performance in a five inch wafer.

• Journal of IKEEE
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• v.7 no.2 s.13
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• pp.236-244
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• 2003

In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than $300{\mu}s$. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a $0.35{\mu}m$ CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is $1.6㎜{\times}3.5㎜$.