• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.12a
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.50-56
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• 2000

The integrated circuit interconnection lines are experimented with patterned ground shields (PGS) at microwave frequencies. Measurement results demonstrate that the PGS can significantly reduce the power loss through the interconnect lines over wide frequency ranges as the PGS shields the lossy silicon substrate. The transmission line characteristics of the PGS interconnect lines are analyzed and identified that the PGS reduces the wave length of the interconnect line.

• Journal of electromagnetic engineering and science
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• v.4 no.2
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• pp.56-62
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• 2004

We present a multi-Gbit/s digital I/O interface based on RF-modulation and capacitive-coupling over an impedance matched transmission line. The RF-interconnect(RFI) can greatly reduce the digital switching noise and eliminate the dc power dissipation over the channel. It also enables reduced signal amplitude(as low as 200 ㎷) with enhanced data rate and affordable circuit overhead. This paper addresses the system advantages and implementation issues of RFI. A prototype on-chip RFI transceiver is implemented in 0.18-${\mu}{\textrm}{m}$ CMOS. It demonstrates a maximum data rate of 2.2 Gbit/s via 10.5-㎓ RF-modulation. The RFI can be very instrumental for future high-speed inter- and intra-ULSI data links.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.188-188
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Meta Oxide Semiconductor) based electronic devices, the electronic devices, become much faster and smaller size that are promising property of semiconductor market. However, very narrow interconnect line width has some disadvantages. Deposition of conformal and thin barrier is not easy. And metallization process needs deposition of diffusion barrier and glue layer for EP/ELP deposition. Thus, there is not enough space for copper filling process. In order to get over these negative effects, simple process of copper metallization is important. In this study, Cu-V alloy layer was deposited using of DC/RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane SiO2/Si bi-layer substrate with smooth surface. Cu-V film's thickness was about 50 nm. Cu-V alloy film deposited at $150^{\circ}C$. XRD, AFM, Hall measurement system, and AES were used to analyze this work. For the barrier formation, annealing temperature was 300, 400, $500^{\circ}C$ (1 hour). Barrier thermal stability was tested by I-V(leakage current) and XRD analysis after 300, 500, $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However vanadium-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Therefore thermal stability of vanadium-based diffusion barrier is desirable for copper interconnection.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.53-58
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• 2012

A new on-wafer de-embedding method using thru, short and open patterns sequentially is proposed to eliminate the errors of conventional methods. This "thru-short-open" method is based on the removal of the coupling admittance between input and output interconnect dangling legs. The increase of the de-embedding effect of the lossy coupling capacitance on the cutoff frequency in MOSFETs is observed as the gate length is scaled down to 45 nm. This method will be very useful for accurate RF measurements of nano-scale MOSFETs.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.6
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• pp.121-127
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• 2004

The controller area network(CAN) was originally developed to support cheap and rather simple automative applications, However, because of the its performance and low cost, it is also being considered in automated manufacturing and process control environments to interconnect intelligent devices, such as modem sensors and actuators. This paper presents a new application technology of the developed CAN control modules for the automated doors in building automation system Key pad and RF methods are used to open and close the automated door by the slave CAN module with CAN Protocol. BAS application technology of CAN field bus modules is also presented firstly in our nation.

• Vacuum Magazine
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• v.3 no.1
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• pp.22-31
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• 2016

Although graphene has been considered as one of the promise materials for future logic devices due to extremely high mobility, its applications in electronics have been limited to a few cases such as a flexible interconnect, and RF devices. Furthermore, most of the studies on graphene devices reported unstable operations, claimed to be due to the poor quality of graphene. Nevertheless, recent studies showed that the electrical performance of graphene field effect transistor could be stabilized even with CVD graphene when well-established integration processes to control the interface of graphene were used. These results indicate that as in the case of silicon devices, a proper control of graphene interface is very important for the stable operation of graphene device as well as other 2D material based devices.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.05a
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• pp.397-403
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• 2004

The controller area network(CAN) was originally developed to support cheap and rather simple automative applications, However, because of the its performance and low cost, it is also being considered in automated manufacturing and process control environments to interconnect intelligent devices, such as modem sensors and actuators. This paper presents a new application technology of the developed CAN control modules for the automated doors in building automation system. Key pad and RF methods are used to open and close the automated door by the slave CAN module with CAN protocol. BAS application technology of CAN field bus modules is also presented firstly in our nation.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.163-163
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• 1999

MOSFET, MESFET 그리고 MODFET는 Logic ULSIs, high speed ICs, RF MMICs 등에서 중요한 역할을 하고 있으며, 그것의 gate electrode, contact, interconnect 등의 물질로는 refractory metal을 이용한 CoSi2, MoSi2, TaSi2, PtSi2, TiSi2 등의 효과를 얻어내고 있다. 그중 TiSi2는 비저항이 가장 낮고, 열적 안정도가 좋으며 SAG process가 가능하므로 simpler alignment process, higher transconductance, lower source resistance 등의 장점을 동시에 만족시키고 있다. 최근 소자차원이 scale down 됨에 따라 TiSi2의 silicidation 과정에서 C49 TiSi2 phase(high resistivity, thermally unstable phase, larger grain size, base centered orthorhombic structure)의 출현과 그것을 제거하기 위한 노력이 큰 issue로 떠오르고 있다. 여러 연구 결과에 따르면 PAI(Pre-amorphization zimplantation), HTS(High Temperature Sputtering) process, Mo(Molybedenum) implasntation 등이 C49를 bypass시키고 C54 TiSi2 phase(lowest resistivity, thermally stable phase, smaller grain size, face centered orthorhombic structure)로의 transformation temperature를 줄일 수 있는 가장 효과적인 방법으로 제안되고 있지만, 아직 그 문제가 완전히 해결되지 않은 상태이며 C54 nucleation에 대한 physical mechanism을 밝히진 못하고 있다. 본 연구에서는 증착 시 기판온도의 변화(400~75$0^{\circ}C$)에 따라 silicon 위에 DC/RF magnetron sputtering 방식으로 Ti/Si film을 각각 제작하였다. 제작된 시료는 N2 분위기에서 30~120초 동안 500~85$0^{\circ}C$의 온도변화에 따라 RTA법으로 각각 one step annealing 하였다. 또한 Al을 cosputtering함으로써 Al impurity의 존재에 따른 영향을 동시에 고려해 보았다. 제작된 시료의 분석을 위해 phase transformation을 XRD로, microstructure를 TEM으로, surface topography는 SEM으로, surface microroughness는 AFM으로 측정하였으며 sheet resistance는 4-point probe로 측정하였다. 분석된 결과를 보면, 고온에서 제작된 박막에서의 C54 phase transformation temperature가 감소하는 것이 관측되었으며, Al impuritydmlwhswork 낮은온도에서의 C54 TiSi2 형성을 돕는다는 것을 알 수 있었다. 본 연구에서는 결론적으로, 고온에서 증착된 박막으로부터 열적으로 안정된 phase의 낮은 resistivity를 갖는 C54 TiSi2 형성을 보다 낮은 온도에서 one-step RTA를 통해 얻을 수 있다는 결과와 Al impurity가 존재함으로써 얻어지는 thermal budget의 효과, 그리고 그로부터 기대할 수 있는 여러 장점들을 보고하고자 한다.