• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.295-301
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• 2011

A triple-band transceiver module for 2.3/2.5/3.5 GHz mobile WiMAX, IEEE 802.16e, applications is introduced. The suggested transceiver module consists of RFIC, reconfigurable/multi-resonance MIMO antenna, embedded PCB, mobile WiMAX base band, memory and channel selection front-end module. The RFIC is fabricated in $0.13{\mu}m$ RF CMOS process and has 3.5 dB noise figure(NF) of receiver and 1 dBm maximum power of transmitter with 68-pin QFN package, $8{\times}8\;mm^2$ area. The area reduction of transceiver module is achieved by using embedded PCB which decreases area by 9% of the area of transceiver module with normal PCB. The developed triple-band mobile WiMAX transceiver module is tested by performing radio conformance test(RCT) and measuring carrier to interference plus noise ratio (CINR) and received signal strength indication (RSSI) in each 2.3/2.5/3.5 GHz frequency.

• 한국전자통신학회논문지
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• 제13권5호
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• pp.959-964
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• 2018

본 논문에서는 고주파에서 동작하는 공핍형 SOI MOSFET의 드레인 전류가 유도성 기생성분에 의해서 응답지연이 일어나는 것을 처음으로 확인하였다. 공핍형 SOI MOSFET는 드레인전압 변동에 따른 드레인전류의 응답지연이 발생하기 때문에 일반적인 MOSFET 고주파모델로는 해석할 수가 없다. 이러한 응답지연은 non-quasi-static 효과로 설명될 수 있으며 SOI MOSFET에서는 일반적인 MOSFET에 비해 유도성 기생성분에 의해 응답지연이 크게 발생하게 된다. 본 논문에서 제시한 고주파모델을 이용하여 공핍형 SOI MOSFET의 드레인 응답지연을 잘 표현하는지 확인한다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2002년도 춘계학술발표논문집 (하)
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• pp.1285-1288
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• 2002

Bluetooth wireless technology is a publicly available specification proposed for Radio Frequency (RF) communication for short-range and point-to- multipoint voice and data transfer. It operates in the 2.4GHz ISM(Industrial, Scientific and Medical) band and offers the potential for low-cost, broadband wireless access for various mobile and portable devices at range of about 10 meters. In this paper, we describe the structure and the test results of the bluetooth baseband module we have developed. This module was developed based on IP reuse. So Interface of each module such as link controller UART, and audio CODEC is designed based on ARM7 comfortable processor. We also considered various interfaces of related external chips. The fully synthesizable baseband module was fabricated in a $0.25{\mu}m$ CMOS technology occupying $2.79{\times}2.8mm^2$ area including the ARM TDMI processor. And a FPGA implementation of this module is tested for file and bit-stream transfers between PCs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.317-318
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• 2006

일반적인 CMOS공정으로는 높은 주파수 대역에서 높은 Q factor를 갖는 인덕터를 구현하는데 어렵고 이에 반해 RF ICs는 갈수록 high Q 를 가지는 인덕터가 요구되고 있다. 이를 LTCC 기판 위에 인덕터를 구현했을 때 높은 주파수 대역에서 성능을 알아보기 위해 모의 실험하였다. 인덕터를 설계하는데 있어서 인덕터 코일의 폭, 코일의 두께와 간격이 인덕터의 성능을 결정짓는다는 것을 고려하였고, MEMS 공정을 이용하여 high Q를 갖는 인덕터를 설계하였다. 인덕터의 전체 크기는 $330{\mu}m\;{\times}\;330{\mu}m$에서 선폭은 $30{\mu}m$, 선간의 간격은 $20{\mu}m$로 기판위에 $80{\mu}m$ 높이로 인덕터를 띄어서 설계하였고, 그리고 이를 LTCC 기판위에 high Q 의 인덕터 구현을 위해 simulation 한 결과가 Q값이 50 정도의 크기를 나타냈다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• 대한전자공학회논문지SD
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• 제44권7호통권361호
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• pp.9-15
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• 2007

본 논문에서는 UHF 대역 수동 RFID 태그(UHF-band passive RFID tag) 칩 제작에 필수적인 요소인 쇼트키(Schottky) 다이오드를 CMOS 공정으로 제작하고 크기에 따른 특성을 분석하였으며 이를 이용하여 전압체배기를 설계하였다. 쇼트키 다이오드는 Titanium-Silicon 접합을 이용하여 제작되었으며, $4{\times}10{\times}10\;{\mu}m^{2}$의 면적을 가지는 쇼트키 다이오드는 $20\;{\mu}A$의 전류 구동에 대해 약 0.15 V의 순방향 전압 강하의 우수한 특성을 나타내었다. 역방향 파괴전압(breakdown)은 약 -9 V로 수동 RFID 태그칩의 전압체배기에 사용될 수 있는 충분한 값을 나타내었다. 제작된 쇼트키 다이오드의 소신호 등가모델을 이용하여 다이오드의 크기에 따른 순방향 전압강하와 입력 임피던스간의 trade-off에 대해 분석하였다. 이를 이용하여 제작된 6-단 전압체배기는 900 MHz 주파수, 200mV 최대 입력 전압에 대해 1.3 V이상의 출력 전압 특성을 나타내어 인식거리가 비교적 큰 수동형 태그에 적합한 특성을 나타내었다.

• 한국전기전자재료학회논문지
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• 제18권4호
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• pp.285-296
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• 2005

Reduced pressure chemical vapor deposition technology has been used to study SiGe heterostructure epitaxy and device issues, including SiGe relaxed buffers, proper control of Ge component and crystalline defects, two dimensional delta doping, and their influence on electrical properties of devices. From experiments, 2D profiles of B and P presented FWHM of 5 nm and 20 nm, respectively, and doses in 5×10/sup 11/ ∼ 3×10/sup 14/ ㎝/sup -2/ range. The results could be employed to fabricate SiGe/Si heterostructure field effect transistors with both Schottky contact and MOS structure for gate electrodes. I-V characteristics of 2D P-doped HFETs revealed normal behavior except the detrimental effect of crystalline defects created at SiGe/Si interfaces due to stress relaxation. On the contrary, sharp B-doping technology resulted in significant improvement in DC performance by 20-30 ％ in transconductance and short channel effect of SiGe HMOS. High peak concentration and mobility in 2D-doped SiGe heterostructures accompanied by remarkable improvements of electrical property illustrate feasible use for nano-sale FETs and integrated circuits for radio frequency wireless communication in particular.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.303-317
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• 2013

Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.167-167
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• 2011

Magnetic random access memory (MRAM) is one of the prospective semiconductor memories for next generation. It has the excellent features including nonvolatility, fast access time, unlimited read/write endurance, low operating voltage, and high storage density. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal-oxide semiconductor (CMOS). The MTJ stack is composed of various magnetic materials, metals, and a tunneling barrier layer. For the successful realization of high density MRAM, the etching process of magnetic materials should be developed. Among various magnetic materials, FePt has been used for pinned layer of MTJ stack. The previous etch study of FePt magnetic thin films was carried out using $CH_4/O_2/NH_3$. It reported only the etch characteristics with respect to the variation of RF bias powers. In this study, the etch characteristics of FePt thin films have been investigated using an inductively coupled plasma reactive ion etcher in various etch chemistries containing $CH_4$/Ar and $CH_4/O_2/Ar$ gas mixes. TiN thin film was employed as a hard mask. FePt thin films are etched by varying the gas concentration. The etch characteristics have been investigated in terms of etch rate, etch selectivity and etch profile. Furthermore, x-ray photoelectron spectroscopy is applied to elucidate the etch mechanism of FePt thin films in $CH_4$/Ar and $CH_4/O_2/Ar$ chemistries.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.408-408
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• 2012

It is well known that magnetic random access memory (MRAM) is nonvolatile memory devices using ferromagnetic materials. MRAM has the merits such as fast access time, unlimited read/write endurance and nonvolatility. Although DRAM has many advantages containing high storage density, fast access time and low power consumption, it becomes volatile when the power is turned off. Owing to the attractive advantages of MRAM, MRAM is being spotlighted as an alternative device in the future. MRAM consists of magnetic tunnel junction (MTJ) stack and complementary metal- oxide semiconductor (CMOS). MTJ stacks are composed of various magnetic materials. FePt thin films are used as a pinned layer of MTJ stack. Up to date, an inductively coupled plasma reactive ion etching (ICPRIE) method of MTJ stacks showed better results in terms of etch rate and etch profile than any other methods such as ion milling, chemical assisted ion etching (CAIE), reactive ion etching (RIE). In order to improve etch profiles without redepositon, a better etching process of MTJ stack needs to be developed by using different etch gases and etch parameters. In this research, influences of $O_2$ gas on the etching characteristics of FePt thin films were investigated. FePt thin films were etched using ICPRIE in $CH_4/O_2/Ar$ gas mix. The etch rate and the etch selectivity were investigated in various $O_2$ concentrations. The etch profiles were studied in varying etch parameters such as coil rf power, dc-bias voltage, and gas pressure. TiN was employed as a hard mask. For observation etch profiles, field emission scanning electron microscopy (FESEM) was used.