• Aerospace Engineering and Technology
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• v.6 no.1
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• pp.83-91
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• 2007

An experimental verification of multipactor(MP) discharge for S-band diplexer as a sample DUT for space application by an in-house MP test facility is proposed. The designed diplexer having two BPFs for Rx and Tx is applied to a design of five pole inter-digital cavity type band pass filter with chebyshev response, it has 2.7 % bandwidth centered at 2.232 and 2.055 GHz for Rx, Tx, respectively. To avoid the MP discharge, the accurate design and analysis methods based on 3D EM field analysis are considered. The proposed in-house MP test facility consists of a phase detecting system using a doubly balanced mixer as a simple, low cost and real time MP test method compared with results of previously well-known MP detection systems as cross reference methods. The calculated MP threshold RF input power is 43.13 dBm. The measured one is 43 dBm and 44 dBm for CW, pulsed mode test, respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.5
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• pp.35-41
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• 2004

In computational study on RF(Radio Frequency) plasmas, a 1D fluid models with an advantage of a short computational time are often adopted. However, in order to obtain realistic calculation results under a typical chamber geometry with unequal-sized electrodes, modeling of the plasma space is an issue to be investigated. In this paper, it is focused on that how much a 1D model can approximate a 2D model. 1D fluid models with unequal-sized electrodes, which have spherical and frustum geometry systems, were developed and their results were compared with those of 2D model with Gaseous Electronic Conference cell structure. Behavior of $N_2$ RF plasmas has been simulated using 1D and 2D fluid models and a technique to take account of unequal-sized electrodes in a 1D fluid models has been examined. Features of the plasma density and the electric potential were discussed as characteristic quantities representing the asymmetry of the chamber geometry.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.37-42
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• 2007

This paper reconsiders established power conservation models for ubiquitous sensor networks that use relay nodes instead of direct communication and proposes novel network power consumption model with consideration of the channel level and radio chip level simultaneously. We estimate the effect of minimum hop-count policy in terms of network power consumption through simulation of various situations for low power RF module CC2420. It is observed that maximum RF power and minimum hop-count results in lower energy consumption relatively. Also, in total network energy consumption, which is included re-transmission, minimum hop count policy presents decrease by 33.1% of energy consumption in compare with the conventional model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.1-6
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• 2004

Effective gate resistance, extracted by direct extraction method, is analyzed among various gate length, in nanoscale MOSFET for RFIC. Extracted effective gate resistance is compared to measured data and verified with simplified model. Extracted parameters are accurate to 10GHz. In the same process technology effect has a different kind of gate voltage dependency and frequency dependency compared with general effective gate resistance. Particularly, the characteristic of effective gate resistance before and after threshold voltage is noticeable. When gate voltage is about threshold voltage, effective gate resistance is abnormally high. This characteristic will be an important reference for RF MOSFET modeling using direct extraction method.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.202-211
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• 2000

Utilizing the circuit simulator SPICE, we designed a 1.9GHz CMOS up-conversion mixer and explained in detail the simulation procedures including device modeling for the circuit design. Since the measured characteristics of the chip fabricated using the $0.5{\mu}m$ standard CMOS process had shown a big deviation from the characteristics expected by the original simulations, we tried to figure out the proper reasons for the discrepancies. Simulations considering the discovered problems in the original simulations have shown the validity of the simulation method tried for the design. We have shown that the utilized standard CMOS process can be used for the implementation of the chip characteristics similar to those of the equivalent chip fabricated using the GaAs MESFET process.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.49-55
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• 2015

The inaccuracy of the bias-dependent gate-drain overlap capacitance $C_{gdo}$ simulation in original BSIM4 and BSIM4 macro model using a diode is analyzed in detail. It is found that the accuracy of the macro model is better than of the BSIM4. However, the macro model cannot be used in the linear region. In order to remove the inaccuracy of the conventional models, a new BSIM4 macro model with a physical bias-dependent $C_{gdo}$ equation is proposed and its accuracy is validated in the full bias range.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.10
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• pp.1910-1915
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• 2007

An accurate and simple method to extract equivalent circuit parameters of fully-depleted silicon-on-insulator MOSFETs small-signal modeling operating at RF frequencies including the non-quasi static effects is presented in this article. The advantage of this method is that a unique and physically meaningful set of intrinsic equivalent circuit parameters is extracted by de-embedding procedure of extrinsic elements such as parasitic capacitances and resistances of MOSFETs from measured S-parameters using simple Z- and Y- matrices calculations. The calculated small-signal parameters using the presented extraction method give modeled Y-parameters which are in good agreement with the measured Y-parameters from 0.5 to 20GHz.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.261-264
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• 2004

In this paper, we identify the memory effect of high power(125W) laterally diffused metal oxide-semiconductor(LDMOS) RF Power Amplifier(PA) by two tone IMD measurement. We measure two tone IMD by changing the tone spacing and the power level. Different asymmetric IMD is founded at different center frequency measurements. We propose the Tapped Delay Line-Neural Network(TDNN) technique as the modeling method of LDMOS PA based on two tone IMD data. TDNN's modeling accuracy is highly reasonable compared to the memoryless adaptive modeling method.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.5
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• pp.147-153
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• 2002

In this paper, a substrate network model to be used with BSIM3 MOSFET model for submicron MOSFETs in giga hertz frequencies and its direct parameter extraction with physically meaningful values are proposed. The proposed substrate network model includes a conventional resistance and single inductance originated from ring-type substrate contacts around active devices. Model parameters are extracted from S-parameter data measured from common-bulk configured MOS transistors with floating gate and use where needed without any optimization process. The proposed modeling technique has been applied to various-sized MOS transistors. The substrate model has been validated for frequency up to 300Hz.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.182.2-182.2
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• 2016

Hollow cathode discharge(중공 음극)는 음극 표면에서 발생되는 2차 전자를 이용하여 높은 밀도의 플라즈마를 만들 수 있는 장점이 있다. 전원으로 microwave, RF, DC, pulsed dc등을 사용할 수 있으며 박막의 증착, 식각 등에 응용 가능하다. 물리적 현상으로는 중공 음극 재료 표면 물질의 가열 및 이온 스퍼터링, 2차 전자의 가열, 자기장 인가 구조의 경우 전자 거동이 있다. PIC(particle-in-cell)방식의 모델링과 fluid model을 이용한 방법이 있는데 본 연구에서는 상용 fluid model software인 ESI사의 CFD-ACE+를 사용하여 모델링 하였다. 구동 주파수는 13.56 MHz의 상용 고주파 전원과 보다 낮은 1 MHz, 100 kHz의 수치 모델을 이용하여 HF, MF, LF 영역에서의 동작 특성을 해석하였다. 1차적으로는 가스 유동의 특성을 2D, 3D로 조사하였고 플라즈마 거동은 2차원을 주로 진행하였으며 계산 시간이 오래 거리는 3차원 모델을 하나 만들어 그 특성을 조사하였다.