• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.302-310
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• 2008

This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); the aspect ratio ($R_{h/w}$) of the fin height (h) to fin width (w) of MuGFET is considered with the aid of 3-D device simulations. Since any change in the aspect ratio must consider the trade-off between drivability and short-channel effects, it is shown that optimization of the aspect ratio is essential in designing MuGFET's. It is clearly seen that the triple-gate (TG) FET is superior to the conventional FinFET from the viewpoints of drivability and short-channel effects as was to be expected. It can be concluded that the guideline of w < L/3, where L is the channel length, is essential to suppress the short-channel effects of TG-FET.

• Journal of the Optical Society of Korea
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• v.6 no.4
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• pp.180-184
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• 2002

In this study, we investigated mask errors, photo errors with attenuated phase shift mask and off-axis illumination, and etch errors in dry etch conditions. We propose that total process proximity correction (TPPC), a concept merging every process step error correction, is essential in a lithography process when minimum critical dimension (CD) is smaller than the wavelength of radiation. A correction rule table was experimentally obtained applying TPPC concept. Process capability of controlling gate CD in DRAM fabrication should be improved by this method.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.287-289
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• 2011

본 논문은 인피니언 테크놀로지스의 RC-IGBT (Reverse Conducting Isolated Gate Bipolar Transistor)와 SOI 드라이브 IC(Integrated Circuit)를 사용한 DIL(Dual-In-Line) 구조의 저전력 모듈인 CIPOS TM (Control Integrated POwer System) 제품을 소개한다. 이 전력 모듈은 최적의 게이트 구동회로, 트렌치 필드스톱의 RC-IGBT를 사용하여 기존의 IGBT 와 Diode를 사용하는 구조에서 최소화 된 패키지 크기를 사용하여 높은 효율을 구현할 수 있다. 본 논문을 통하여 인버터의 어플리케이션에 적합하게 설계된 전력모듈에 대한 소개와 그 특징 및 시스템 구성을 위한 고려사항에 대하여 기술하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1292-1294
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• 2007

In this report, the effects of chemical surface treatments of ITO gate electrodes of OTFTs have been studied by using acid and base solutions. As a result, it is observed that the threshold voltage of OTFTs could be influenced and modified by the surface treatments. The device with an ITO gate electrode surface-treated by a base solution shows the lowest threshold voltage of -7.66 V, while the threshold voltages are about -13.51 V and -15.3 V for the devices without a surface treatment and with the acid solution treatment, respectively. It is thought that the work function of ITO electrode surface might be affected by the surface treatments, thereby influencing the threshold voltage.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.634-637
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• 1997

This paper is on the research and development of new SIV(Static Inverter) using IGBT(Insulated Gate Bipolar Transistor) semiconductor for a wide range of electric railway applications. For the simplification and higher controllability, the direct PWM control method with 3level inverter topology was adopted. In the new SIV system, the cost as well as bulk and weight was appreciably reduced about 40% lower than those of conventional SIV, the electrical efficiency was increased above 95% and the audible noise level was less than 65dB. In addition, the THD(Total Harmonic Distortion) factor was below 5% and the voltage fluctuation on a transient state was below 10%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• International Journal of Automotive Technology
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• v.4 no.2
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• pp.57-64
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• 2003

The Intelligent Power Unit (IPU) utilized in Honda's Civic Hybrid Integrated Motor Assist (IMA) system was developed with the aim of making every component lighter, more compact and more efficient than those in the former model. To reduce energy loss, inverter efficiency was increased by fine patterning of the Insulated Gate Bipolar Transistor (IGBT) chips, 12V DC-DC converter efficiency was increased by utilizing soft-switching, and the internal resistance of the IMA battery was lowered by modifying the electrodes and the current collecting structure. These improvements reduced the amount of heat generated by the unit components and made it possible to combine the previously separated Power Control Unit (PCU) and battery cooling systems into a single system. Consolidation of these two cooling circuits into one has reduced the volume of the newly developed IPU by 42% compared to the former model.

• Journal of Korean Society for Quality Management
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• v.47 no.1
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• pp.151-162
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• 2019

Purpose: This study is in order to secure high quality of military supplies, it is important to secure design quality in the development phase. I will review how to establish a quality assurance system in the development phase based on the author's seminar presentation contents and application example of Hanwha Systems Co., Ltd. Methods: To guarantee design quality in the development phase, in 2002, quality assurance system that is adequate for SQA(Software Quality Assurance)'s requirements of CMM(Capability Maturity Model) was conduct. In 2009, based on the CMMI(Capability Maturity Model Integration) Level 5, there has been continuous and reenforced quality assurance activities. Results: By suggesting the construction and a case study on application of R&D quality assurance, it would be helpful for companies aiming to construct or enhance quality assurance system. Conclusion: To secure high quality for military supplies, a development QA system should be established to secure quality in the development phase. In addition, Total life cycle QA system for development, mass production and operation phase should be reestablished.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07a
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• pp.665-667
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• 2005

VIATRON TECHNOLOGIES has developed FE-RTP system that enables LTPS LCD and AMOLED manufacturers to produce poly-Si films at low cost, high throughput, and high yield. The system employs sequential heat treatment methods using temperature control and rapid thermal processor modules. The temperature control modules provide exceptionally uniform heating and cooling of the glass substrates to within ${\pm}2^a\;C$. The rapid thermal process that combines heating with field induction accelerates the treatment rates. The new FE-RTP system can process $730{\times}920mm$ glass substrates as thin as 0.4 mm. The uniform nature of poly-Si films produced by FE-RTP resulted in AMOLED panels with no laser-Muras. Furthermore, FE-RTP system also showed superior performances in other heat treatment processes involved in poly-Si TFT fabrications, such as dopant activation, gate oxide densification, hydrogenation, and pre-compaction.

• Journal of information and communication convergence engineering
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• v.14 no.1
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• pp.40-44
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• 2016

The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T_ILD and dielectric constant ε_r of the inter-layer distance (ILD), the doping concentration N_d (N_a), and length L_g of the channel, and the side-wall length L_SW where the stacked FETs are coupled are studied. When N_d (N_a) < 10¹⁶ cm^-3 and L_SW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N_d (N_a) > 10¹⁶ cm^-3 or L_SW > 20 nm, the shift decreases and increases, respectively. M3INVs with T_ILD ≥ 50 nm and ε_r ≤ 3.9 can neglect the interaction between the stacked FETs, but when T_ILD or ε_r do not meet the above conditions, the interaction must be taken into consideration.