• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.29-36
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• 2016

Recently a new class of quantum gate called $NCV-{\mid}v_1$ > library with low cost realizable potentialities is being watched with keen interest. The $NCV-{\mid}v_1$ > MCT gate is composed of AND cascaded-$CV-{\mid}v_1$ > gates to control the target qudit and its adjoint gates to erase junk ones. This paper presents a new symmetrical duality library named $NCV^{\dag}-{\mid}v_1$ > library corresponding to $NCV-{\mid}v_1$ > library. The new $NCV^{\dag}-{\mid}v_1$ > library can be operated on OR logic under certain conditions. By using both the $NCV-{\mid}v_1$ > and $NCV^{\dag}-{\mid}v_1$ > libraries it is possible to realize MPMCT gates, SOP and POS type synthesis of quantum logic circuits with extremely low cost, and expect dual gate property caused by different operational attributes with respect to forward and backward operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.56-65
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• 2006

The Quantum-dot Cellular Automata (QCA) can be considered as a candidate for the next generation digital logic implementation technology due to their small feature sizes and ultra low power consumption. Up to now, several designs using Uh technology have been proposed. However, we found not all of the designs function properly. Furthermore, no general design guidelines have been proposed so far. A straightforward extension of a simple functional design pattern may fail. This makes designing a large scale circuits using QCA technology an extremely time-consuming process. In this paper, we show several critical vulnerabilities related to unbalanced input paths to QCA gates and sneak noise paths in QCA interconnect structures. In order to make up the vulnerabilities, a disciplinary guideline will be proposed. Also, we present a fast adder which has been designed by the discipline, and verified to be functional by the simulation.

• ETRI Journal
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• v.17 no.4
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• pp.1-12
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• 1996

A novel body-tied silicon-on-insulator(SOI) n-channel metal-oxide-semiconductor field-effect transistor with grounded body electrode named GBSOI nMOSFET has been developed by wafer bonding and etch-back technology. It has no floating body effect such as kink phenomena on the drain current curves, single-transistor latch and drain current overshoot inherent in a normal SOI device with floating body. We have characterized the interface trap density, kink phenomena on the drain current ($I_{DS}-V_{DS}$) curves, substrate resistance effect on the $I_{DS}-V_{DS}$ curves, subthreshold current characteristics and single transistor latch of these transistors. We have confirmed that the GBSOI structure is suitable for high-speed and low-voltage VLSI circuits.

• Progress in Superconductivity
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• v.4 no.1
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• pp.37-41
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• 2002

In this work. we have designed two different kinds of Rapid Single Flux Quantum (RSFQ) OR-gates. One was based on the already developed RSFQ cells and the other was aimed to develop a more compact version. In the first circuit, we used a combination of two D Flip-Flops and a merger and in the other circuit we used a combination of RS Flip-Flops and Confluence Buffer. We tested the circuit performance by using the simulation tools, Xic and Wrspice. We obtained the operation margins of the circuit elements by a margin calculation program, and we obtained the minimum operation margins of $\pm$30%. The circuits were laid out, aimed to fabricate by using the existing KRISS Nb process. KRISS Nb process includes the $Nb／Al_2$$O_3$／Nb trilayer fabricated by DC magnetron sputtering and the reactive ion etching technique for the definition of the features. The major tools used in the layouts were Xic and L-meter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.457-460
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• 1998

Present paper is devoted to the brief analysis of the present state and the prospects for the future of technology of the high frequency devices and high speed integrated circuits based on the $A_{3}B_{5}$ semiconductor compounds, including the $A_{3}B_{5}$-heterostructures, in the republics of the former USSR. tunneling quantum well-structures were widely used.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.34-40
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• 2018

Traditionally, many researchers have conducted research on terahertz technology utilizing optical devices such as lasers. However, nanometer-scale electronic devices using silicon or III-V compound semiconductors have received significant attention regarding the development of a terahertz system owing to the rapid scaling down of devices. This enables an operating frequency of up to approximately 0.5 THz for silicon, and approximately 1 THz for III-V devices. This article reviews the recent trends of terahertz monolithic integrated circuits based on several electronic devices such as CMOS, SiGe BiCMOS, and InP HBT/HEMT, and a particular quantum device, an RTD.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.29-32
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• 2023

양자 컴퓨터의 연산 성능이 알려지면서 기존 암호 시스템이 붕괴될 것이라 예상한다. 앞선 많은 연구들은 공격 대상 암호에 대해 양자회로로 구현하고 공격에 필요한 양자자원을 추정하였지만 암호를 공격하기 위해서는 대규모 양자컴퓨터의 동작을 요구한다. 뿐만 아니라 내결함성 양자 컴퓨터에서 유효한 결과를 얻기 위해서는 오류 정정이 필수적이며 오류 정정에도 양자 자원을 소비하며 결과적으로 더 큰 규모의 양자컴퓨터가 필요하고 크기가 커질수록 오류가 증가한다. 이러한 내결함성 대규모 양자회로에서 T 게이트를 구현하는 것이 다른 게이트를 구현하는 것 보다 어렵고 T-depth가 회로의 실행시간에 큰 영향을 미친다. 본 논문에서는 T-depth 최적화 도구 및 T-depth 감소 기법을 적용한 방식을 조사하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.183-187
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• 2023

양자 컴퓨터가 빠르게 발전됨에 따라 기존의 공개키 암호들이 기반하고 있는 난제인 소인수분해, 이산로그 문제를 다항 시간 안에 풀 수 있는 Shor 알고리즘에 의해 기존 암호의 보안 강도 약화 및 무력화 시기가 다가오고 있다. NIST에서는 양자 컴퓨터 시대에 대비하여 양자 컴퓨터가 등장하더라도 안전한 암호인 양자내성암호에 관한 공모전을 개최하였다. 양자 컴퓨터 환경에서 암호 분석을 통해 암호의 보안 강도를 확인할 수 있는데, 이를 위해서는 암호를 양자회로로 구현해야한다. 본 논문에서는 NIST PQC 공모전의 4 라운드 후보 알고리즘인 HQC (Hamming Quasi-Cyclic)의 PKE (Public Key Encryption) 버전에 대한 키 생성 및 인코딩 연산 중 핵심 역할을 하는 바이너리 필드 산술과shortened Reed-Solomon 코드의 인코딩 연산에 대한 최적화된 양자회로 구현을 제안하고, 이를 위해 필요한 자원을 추정한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.91-105
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• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.71-74
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• 1999

We have fabricated high-T$_c$ superconducting YBa$_2Cu_3O_{7-{\delta}}\;/SrTiO_3/\;YBa_2Cu_3O_{7-{\delta}}$ (YBCO/STO/YBCO) multilayer structure on (001) $SrTiO_3$ substrate by using pulsed laser deposition technique for applying to ground plane of single flux quantum digital circuits. In this structure, the top and bottom YBCO layers were connected through the holes in the STO insulating layer. The critical temperature of the two YBCO layers connected each other was 86 K after annealing at 500 $^{\circ}C$ in $O_2$ atm for about 60 hr. This result shows that the annealing process is very important fabricating YBCO/STO/YBCO multilayer structure An experiment to optimize the fabrication process of YSCO/ST0/YBCO multilayer structure with good quality is in progress.