• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2003년도 봄 학술발표회 논문집
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• pp.521-528
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• 2003

In this study, a newly modified soil nailing technology called as the NDB(New Down and Board) soil nailing system is introduced. To improve the trafficability, workability, and economical efficiency, SMC(Sheet Molding Compound) board is adopted instead of using the concrete block facing. The SMC board has a distinct advantage of showing a fine view by directly coating with any kind of environmental photos. Composite material properties of the SMC board and cement grout are distinguished features of the NDB soil nailing system. In the present study, both laboratory tests(bending and punching failure tests) and field pull-out tests are carried out to analyze the behavior characteristics of the NDB soil nailing system, including the stress and strain distribution.

• 전자공학회논문지SC
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• 제39권2호
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• pp.140-145
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• 2002

본 논문은 단락회로 전류를 없애기 위한 CMOS 버퍼회로에 대한 것이다. 최종 구동소자는 풀-업 PMOS와 풀-다운 NMOS로 구성하고 이를 구동하기 위해 두가지 경로를 입력신호로 선택되도록 하였다. 이러한 기법으로 최종 구동회로가 짧은 시간동안 tri-state가 되어 단락회로 전류를 차단하였다. 모의 실험결과 전원전압 3.3V에서 전력-지연 곱을 기존의 Tapered 버퍼[1]와 비교하여 약 42% 줄일 수 있었다

• Transactions on Electrical and Electronic Materials
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• 제14권3호
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• pp.116-120
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• 2013

This paper proposes a novel RF MEMS dc-contact switch with stiff membrane on a quartz substrate. The uniqueness of this work lies in the utilization of a seesaw mechanism to restore the movable part to its rest position. The switching action is done by using separate pull-down and pull-up electrodes, and hence operation of the switch does not rely on the elastic recovery force of the membrane. One of the main problems faced by electrostatically actuated MEMS switches is the high operational voltages, which results from bending of the membrane, due to internal stress gradient. This is resolved by using a stiff and thick membrane. This membrane consists of flexible meanders, for easy movement between the two states. The device operates with an actuation voltage of 6.43 V, an insertion loss of -0.047 dB and isolation of -51.82 dB at 2 GHz.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술대회 논문집 전문대학교육위원
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• pp.113-116
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• 2003

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In this paper, proposes a method for efficiently generating test pattern which detect faults in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• 전기학회논문지P
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• 제53권1호
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• pp.22-27
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• 2004

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• 한국지구과학회지
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• 제27권7호
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• pp.757-767
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• 2006

Alluvial-plain deposits in the southeastern part of the Eumsung Basin (Cretaceous) are characterized by coarse-grained channel fills encased in purple siltstone beds. It represents distinct channel geometry, infill organization, and variations in facies distribution. The directions of paleocurrent, sedimentary facies changes, and channel-fill geometry can be used to reconstruct a channel network in the alluvial system developed along the southeastern margin of the basin. The channel-fill facies represent downstream changes: 1) down-sizing and well-sorting in clast and martix of channel fills and 2) internal organization of scour fill or gravel lag and overlying cross-stratified, planar-stratified beds. These findings suggest multiple stages of channel-filling processes according to flooding and subsequent stream flows. In the small-scale pull-apart Eumsung Basin (${\sim}7{\times}33km^2$ in area), vertical-stacked alluvial architecture of the coarse-grained channel fills encased in purple siltstone is expected to result from episodic channel shifting under a rapidly subsiding setting.

• 전자공학회논문지A
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• 제33A권2호
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• pp.184-195
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• 1996

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.74-76
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• 2004

A Half-VDD Voltage(VHDD) Generator using PMOS pull-up transistor and NMOS pull-down transistor was newly proposed for low-voltage DRAMs. The driving current was increased and the power-on settling time was reduced in the new circuit. The newly proposed VHDD generator worked successfully at VDD at 1.5V and fabricated using 0.18um CMOS twin-well technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.657-658
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• 2006

A Novel level-shifter circuit for Display Panel Driver is presented. A Proposed level-shifter is for the high speed and high-voltage driving capability. In order to achieve this purpose, the proposed level-shifter restricts and separates the Vgs of the output driver's pull-up PMOS and pull-down NMOS with Zener diode. And a speed-up PMOS transistor is introduced to reduce delay. The control signal of speed-up PMOS was designed by bootstrapping method to minimize the gate to source (Vgs) voltage to avoid Vgs breakdown.

• 전자공학회논문지C
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• 제34C권1호
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• pp.1-11
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• 1997

A BiCMOS circuit consists of the CMOS part which performs the logic function, and the bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential beavior. Also, stuck-on faults enhanced IDDQ (quiscent power supply current) at steady state. In this paper, a method is proposed which efficiently generates test patterns to detect stuck-open faults and stuck-on faults in BiCMOS circuits. The proposed method divides the BiCMOS circuit into pull-up part and pull-down part, and generates test patterns detect faults occured in each part by structural property of the BiCMOS circuit.