• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.7-14
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• 2005

This paper presents a new low power BIST TPG scheme. It uses a transition monitoring window (TMW) that is comprised of a transition monitoring window block and a MUX. When random test patterns are generated by an LFSR, transitions of those patterns satisfy pseudo-random gaussian distribution. The Proposed technique represses transitions of patterns using a k-value which is a standard that is obtained from the distribution of U to observe over transitive patterns causing high power dissipation in a scan chain. Experimental results show that the Proposed BIST TPG schemes can reduce scan transition by about $60\%$ without performance loss in ISCAS'89 benchmark circuits that have large number scan inputs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.707-714
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• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.147-155
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• 2017

A new endurance test-pattern generation on NAND-flash memory is proposed to improve test cost. We mainly focus on the correlation between the data-pattern and the device error-rate during endurance testing. The novelty is the development of testing method using quasi-random pattern based on device architectures in order to increase the test efficiency during time-consuming endurance testing. It has been proven by the experiments using the commercial 32 nm NAND flash-memory. Using the proposed method, the error-rate increases up to 18.6% compared to that of the conventional method which uses pseudo-random pattern. Endurance testing time using the proposed quasi-random pattern is faster than that of using the conventional pseudo-random pattern since it is possible to reach the target error rate quickly using the proposed one. Accordingly, the proposed method provides more low-cost testing solutions compared to the previous pseudo-random testing patterns.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.803-806
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• 2007

Since the different characteristics from the PRNG (Pseudo Random Number Generator) or various deterministic devices such as arithmetic processing units, new concepts and test methods should be suggested in order to test TRNG (Ture Random Number Generator). Deterministic devices can be covered by ATPG (Automatic Test Pattern Generation), which uses patterns generated by cyclic shift registers due to its hardware oriented characteristics, pure random numbers are not possibly tested by automatic test pattern generation due to its analog-oriented characteristics. In this paper, we studied and analyzed a hardware/software combined test method named Diehard test, in which we apply continuous pattern variation to check the statistics. We also point out the considerations when making random number tests.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.91_92
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• 2009

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.796-800
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• 2011

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• Journal of Life Science
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• v.14 no.1
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• pp.32-37
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• 2004

A portion of ribosomal internal transcribed spacer (ITS) 2 was sequenced from the samples of Pseudo nitzschia (P. deticatissima, P. multiseries, P. pungens and P. subfraudulenta) to investigate the genetic characteristics by measuring tile magnitude of genetic diversity and the degree of similarity coefficient using random amplified polymorphic DNAs (RAPD)-PCR patterns. The phylogenetic trees inferred from the genetic distance analyses showed the placement of P. delicatissima formed a quite long distance from p. P. multiseries, P. pungens, and even P. subfraudulenta. The phylogenetic tree from RAPD patterns showed that P. multiseries and P. pungens had dissimilarity coefficient of 0.31, while P. delicatissima and three species of Pseudo-nitzschia had that of 0.81. It is likely thought that the genetic position of P. delicatissima formed far from P. multiseries, P. punges, and P. subfraudulenta. These results imply that ITS2 region is expected to support a useful molecular characters for recognizing at the species level and for even discriminating P. multiseries from P. pungens. RAPD method also will be used to differentiate the species of Pseudo-nitzschia in a short time.

• Journal of Korean Society for Atmospheric Environment
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• v.6 no.1
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• pp.1-10
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• 1990

The purpose of the study was to analyze air quality in underground shopping centers using pattern recognition methods. In order to perform this, the concentraion of air pollutants such as $CO, NO_2, NO_x, SO_2$, and particulate matters was measured at the 11 different shopping centers in Seoul metropolitan area and the total of 47 samples were obtained at random based on the size of shopping centers. To introduce a new concept of the "average concentration" for the indoor air quality analyses, the various multivariate statistical analyses have been studied. Thus, a cluster analysis was applied to separate the samples into pseudo-patterns and a disjoint principal component analysis was used to generate homogeneous patterns after removing outliers from the pseudo-patterns. The 6 homogeneous patterns were then obtained as follows:the first pattern was a group of clean sites;the second a group of sites having high dust concentration;the third a group of sites having high dust and $NO_x$ concentration;the fourth a group of sites having low dust and $SO_2$ concentraion and high CO concentration;the fifth a group of sites having high $NO_2 and SO_2$ concentration;and the final a group of miscellaneous sites. Thus, the average concentration could be estimated for each pattern.h pattern.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.5
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• pp.15-24
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• 2009

This paper proposes an effective low power BIST architecture using the pattern mapping method for 100% fault coverage and the transition freezing method for making high correlative low power patterns. When frozen patterns are applied to a circuit, it begins to find a great number of faults at first. However, patterns have limitations of achieving 100% fault coverage due to random pattern resistant faults. In this paper, those faults are covered by the pattern mapping method using the patterns generated by an ATPG and the useless patterns among frozen patterns. Throughout the scheme, we have reduced an amount of applied patterns and test time compared with the transition freezing method, which leads to low power dissipation.