• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.319-321
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• 2006

본 논문에서는 다양한 캐리 전달 방식(carry propagation scheme)이 단일 가산기 설계를 위하여 복합적으로 사용되는 가산기 구조물 제안하며. 이를 통하여 보다 향상된 delay-area trade-off 점들을 갖는 설계공간을 생성한다. 제안된 구조의 가산기는 각기 다른 캐리전달 방식의 하부 가산기 블록들을 캐리 입/출력 신호를 선형으로 연결한 구조이며, 기존의 단일 캐리전달 방식의 가산기와 달리, 다양한 delay-area trade-off 특성을 갖는 여러 종류의 캐리전달 방식을 비트 수준에서 조합하여 사용함으로써 보다 섬세한 delay-area 설계공간을 생성해낼 수 있다. 그러나, 제안된 가산기 구조의 설계공간은 다양한 캐리전달 방식이 비트 수준에서 할당되므로, 할당가능한 설계 조합은 설계하고자 하는 가산기의 비트 폭과 고려하는 캐리전달 방식의 수에 비례하여 폭발적으로 증가하게 된다. 따라서, 제안된 가산기의 효율적이며, 자동화된 설계공간 탐색 방범이 요구된다. 본 논문에서는 이를 해결하기 위하여 정수 선형 프로그래밍 (Integer Linear Programming, ILP) 방법을 이용하여 제안한 가산기의 최적화 문제를 형식화함으로써 효과적인 설계공간의 탐색 방법을 제안하였다.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.491-494
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• 2006

Kalman filtering (KF) is hard to be applied to the SINS (Strap-down Inertial Navigation System)/RDSS (Radio Determination Satellite Service) integrated navigation system directly because the time delay of RDSS positioning in active mode is random. BP (Back-Propagation) Neuron computing as a powerful technology of Artificial Neural Network (ANN), is appropriate to solve nonlinear problems such as the random time delay of RDSS without prior knowledge about the mathematical process involved. The new algorithm betakes a BP neural network (BPNN) and velocity feedback to aid KF in order to overcome the time delay of RDSS positioning. Once the BP neural network was trained and converged, the new approach will work well for SINS/RDSS integrated navigation. Dynamic vehicle experiments were performed to evaluate the performance of the system. The experiment results demonstrate that the horizontal positioning accuracy of the new approach is 40.62 m (1 ${\sigma}$), which is better than velocity-feedback-based KF. The experimental results also show that the horizontal positioning error of the navigation system is almost linear to the positioning interval of RDSS within 5 minutes. The approach and its anti-jamming analysis will be helpful to the applications of SINS/RDSS integrated systems.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.127-131
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• 2009

In the digital waveguide theory, traveling waves are represented by general solution to the wave equation that is second-order linear partial differential equation. The movement of these waves can be implemented using only delay lines. An unit delay in the general digital waveguide describes a sampling time interval. However, in the space-based digital waveguide the unit delay implies the spatial sampling distance. In consideration of these differences between two models, it is known that the space-based digital waveguide model is adequate to synthesize pitch-shifted sounds such as vibrato because the propagation distance can be directly control. In this paper, the time-based digital waveguide model which also synthesizes pitch-shifted sounds is proposed and compared with space-based digital waveguide.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.11
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• pp.1564-1570
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• 2015

This paper intends to suggest a sensing circuit of PWM voltage for a motor emulator operated in the inverter. In the emulation of the motor using a power converter, it is necessary to measure instantaneous voltage at the PWM voltage loaded from the inverter. Using a filter can generate instantaneous voltage, while it is difficult to follow the rapidly changing inverter voltage caused by the propagation delay and signal attenuation. The method of measuring the duty of PWM using FPGA can generate output voltage from the one-cycle delay of PWM, while the cost of hardware is increasing in order to acquire high precision. This paper suggests a PWM voltage sensing circuit using the analogue system that shows high precision, one-cycle delay of PWM and low-cost hardware. The PWM voltage sensing circuit works in the process of integrating input voltage for valid time by comparing levels of three-phase PWM input voltage, and produce the output value integrated at zero vector. As a result of PSIM simulation and the experiment with the produced hardware, it was verified that the suggested circuit in this paper is valid.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.484-492
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• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1141-1144
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• 1998

A new design methodology for the shortchannel CMOS IC-package is presented. It is developed by representing the package inductance with an effective lumpedinductance. The worst case maximum-simultaneous-switching noise (SSN) and gate propagation delay due to the package are modeled in terms of driver geometry, the maximum number of simultaneous switching drivers, and the effective inductance. The SSN variations according to load capacitances are investigated with this model. The package design techniques based on the proposed guidelines are verified by performing HSPICE simulations with the $0.35\mu\textrm{m}$ CMOS model parameters.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.59-62
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• 2000

본 논문에서는 실측 데이터를 기준으로 9가지의 다양한 모델을 제안한 JTC(Joint Technical Committee) 모델을 전송 채널 모델로 채택하여 채널의 PDP(Power Delay Profile)의 불규칙성 따른 OFDM (Orthogonal Frequency Division Multiplexing) 통신 시스템의 성능을 분석하였다 전송 채널의 불규칙성은 Main profile의 길이, Peak 위치, Echo profile의 지연 시간, 그리고 Echo profile의 강도로 분류하여 각각에 따른 PDP를 설정하여 각 모델에 따른 OFDM 시스템의 성능 분석을 하였다.

• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.94.4-94
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• 2001

An acoustic ranging system was applied for reckoning the location of an agricultural vehicle in the field. The system has a number of fixed stations and a mobile station such as an agricultural vehicle. The mobile station comprises a radio frequency modulator-demodulator (RF MODEM), a buzzer, and a personal computer. The fixed station comprises an (RF MODEM), a microphone, an amplifier for the microphone, and a personal computer with a soundboard. The mobile station transmits a 7-bit ASCII code and, activates the buzzer simultaneously. The propagation delay time at the fixed station is caused by the difference ...

• Journal of Ocean Engineering and Technology
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• v.11 no.4
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• pp.180-188
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• 1997

This paper proposes a new efficient MAC(Media Access Control) protocol to establish the ultrasonic communication network for underwater vehicles, which ensures a certain level of maximum throughput regardless of the propagation delay of ultrasonic and allows fast data transmission through the multiple ultrasonic communication channel. A MAC protocol for underwater communication network that allows 'peer-to-peer' communication between a surface ship and multiple underwater systems is designed, and the proposed control protocol is implemented for its verification.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.8
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• pp.52-59
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• 1998

New types of PFD (phase-frequency detector) are proposed with reset time and propagation delay reduced. The perfomrance of our proposed PFDs are confirmed by SPICE simulation with 0.8.mu.m CMOS process parameter. As a result of simulation, the reset time of PFDs are 0.32 nsec and 0.030 nsec in capture-process. The proposed PFDs can be used in hihg-speed phase-licked loop (PLL).