• Smart Media Journal
• /
• v.4 no.3
• /
• pp.16-23
• /
• 2015

As the IT technology advances, data processing system is required to handle and process large amounts of data. However, the existing On-Disk system has limit to process data which increase rapidly. For that reason, the In-Memory system is being used which saves and manages data on the fast memory not saving data into hard disk. Although it has fast processing capability, it is necessary to use the fault tolerance techniques in the In-Memory system because it has a risk of data loss due to volatility which is one of the memory characteristics. These fault tolerance techniques lead to performance degradation of In-Memory system. In this paper, we classify the data into Hot and Cold data in consideration of the data usage characteristics in the In-Memory system and propose compound backup technique to ensure data persistence. The proposed technique increases the persistence and improves performance degradation.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.2
• /
• pp.1073-1083
• /
• 2015

As an empirical study focused on how transactive memory concept influence the four processes of knowledge growth, this study aimed at explaining the function of transactive memory in the dynamic process of knowledge growth. To verify the research model, this study carried out a path analysis of 130 team memebers and as a result, part of the team transactive memory measurements does affect the knowledge growth. Consequentially, transactive memory especially based on team level, is relevant with knowledge growth. According to team level, this study targeted at the team members, and by adopting the team transactive memory concept in Cognitive Psycology, theoretically explained and analysed how to approach personal knowledge in internal organizations. To accelerate the knowledge process, the work should be modified collaboratively by trusting the team members' duty relations more than specialized knowledge. Furthermore, managers had better assign team members the work where they can make the most of their personal knowledge, and this study presented that the whole team performance could be improved by doing that.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.21 no.4
• /
• pp.89-100
• /
• 2011

Physical memory analysis has been an issue on a field of live forensic analysis in digital forensics until now. It is very useful to make the result of analysis more reliable, because record of user behavior and data can be founded on physical memory although process is hided. But most memory analysis focuses on windows based system. Because the diversity of target system to be analyzed rises up, it is very important to analyze physical memory based on other OS, not Windows. Mac OS X, has second market share in Operating System, is operated by loading kernel image to physical memory area. In this paper, We propose a methodology for physical memory analysis on Mac OS X using symbol information in kernel image, and acquire a process information, mounted device information, kernel information, kernel extensions(eg. KEXT) and system call entry for detecting system call hooking. In additional to the methodology, we prove that physical memory analysis is very useful though experimental study.

• Communications for Statistical Applications and Methods
• /
• v.9 no.3
• /
• pp.577-594
• /
• 2002

For the estimation and test of long memory feature in volatilities of stock indices and individual companies semiparametric approach, Geweke and Porter-Hudak (1983), is employed. Empirical study supports the strong evidence of volatility persistence in Korean stock market. Most of indices and individual companies have the feature of long term dependence of volatility. Hence the short memory models are unable to explain the volatilities in Korean stock market.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.8
• /
• pp.23-32
• /
• 1998

In this paper, we propose a memory compiler to genrate embedded RAMs and ROMs for ASIC chips. We design the leaf cells to be compsoed of memory blocks. The compiler is built using tile-based method to simplify routing. The compiler can genrate any memory layouts to satisfy 64 to 4096 words and 4 to 256 bits per word. The technology we used here is 0.8.mu.m single poly double metal CMOS process. The address access time and power consumption are verifie dthrough the HSPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.9
• /
• pp.1102-1107
• /
• 1988

We describe a volume holographic associative memory using photorefractive material and conventional planar mirror. Multiple hologram is generated with two angular multiplexed writing beams and Fourier transformed object beam in Ba Ti O3 crystal at 0.6328 um. Complete image can be recalled successfully by partial input of the original stored image without any additional thresholding and optical feedback process. It is proved that our system is useful for optical implementation of real-time associative memory and location addressable memory.

• Journal of Ginseng Research
• /
• v.20 no.3
• /
• pp.226-232
• /
• 1996

This study was performed to investigate the effect of red ginseng extract including some vitamin B groups as test drug on learning and memory in mice. Single and repeated administrations of the test drug improved the acquisition and the process of consolidation in the tests using step-through and step-down apparatus, indicating this test drug improved learning and memory. However, the test drug did not improve scopolamine-induced amnesia. These results suggest that test drug may be useful as a nootropic agent.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.4
• /
• pp.187-189
• /
• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• Journal of Information Processing Systems
• /
• v.14 no.2
• /
• pp.499-509
• /
• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.34 no.9C
• /
• pp.880-886
• /
• 2009

Recently, the memory is used in many electronic devices, thus, the many researchers make a study of the memory. To increase a storage capacity per memory block, the researchers study for reducing the fabrication process of memory and multi-level cell memory which is storing more than 2-bits in a cell. However, the multi-level cell memory has low bit-error rates by various noises. In this paper, we study the noise of multi-level cell memory, and we propose the channel model of multi-level cell memory.