Browse > Article

Channel Modeling for Multi-Level Cell Memory  

Park, Dong-Hyuk (숭실대학교 정보통신전자공학부 정보저장 및 통신 연구실)
Lee, Jae-Jin (숭실대학교 정보통신전자공학부 정보저장 및 통신 연구실)
Abstract
Recently, the memory is used in many electronic devices, thus, the many researchers make a study of the memory. To increase a storage capacity per memory block, the researchers study for reducing the fabrication process of memory and multi-level cell memory which is storing more than 2-bits in a cell. However, the multi-level cell memory has low bit-error rates by various noises. In this paper, we study the noise of multi-level cell memory, and we propose the channel model of multi-level cell memory.
Keywords
Multi-Level Cell Memory; Memory Channel; Coupling Effect;
Citations & Related Records
연도 인용수 순위
  • Reference
1 B. Polianskikh and Z. Zilie, 'Induced error-correcting code for 2bit-per-cell multi-level DRAM,' Proceeding of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, Vol. 2, pp. 352-355, Aug., 2001
2 H. Nobukata et al., 'A 144-Mb, Eight-level NAND flash memory with optimized pulsewidth programming,' IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, pp. 682-690, May, 2000   DOI   ScienceOn
3 T. Hara et al., 'A 146-mm2 8-Gb multi-level NAND flash memory with 70-nm CMOS technology,' IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, pp. 161-169, Jan., 2006   DOI   ScienceOn
4 M. Grossi, M. Lanzoni, and B. Ricco, 'Program schemes for multilevel flash memories,' Proceedings of the IEEE, Vol. 91, No. 4, pp. 594-601, April, 2003   DOI   ScienceOn
5 H Chang et al., 'Multi-level memory systems using error control codes,' IEEE International Symposium on Circuits and Systems (ISCAS), pp. II-393-II-396, May, 2004
6 S. Fe et al., 'Multilevel flash memory on-chip error correction based on trellis coded modulation,' IEEE International Symposium Circuits and Systems (ISCAS), pp. 1443-1446, May, 2006
7 R. Bez et al., 'Introduction to flash memory,' Proceeding of the IEEE, Vol. 91, No. 4, pp. 489-502, April, 2003   DOI   ScienceOn
8 N. Shibata, and T. Tanaka, 'Semiconductor memory device for storing multivalued data,' U.S. Patent 6 657 891, Dec., 2, 2003
9 T. Cho et al., 'A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb signal- level modes,' IEEE Journal of Solid-State Circuits, Vol. 36, No. 11, pp. 1700-1706, Nov., 2001   DOI   ScienceOn
10 Y. Hisamune et al., 'A high capacitive-coupling ratio (HiCR) cell for 3 v-only 64 Mbit and future flash memories,' IEEE International Electron Device Meeting Technical Digest 1993, pp. 19-22, Dec., 5-8 1993
11 J. Lee, S. Hur, and J. Choi, 'Effects of floating-gate interference on NAND flash memory cell operation,' IEEE Electron Device Letters, Vol. 23, No. 5, pp. 264-266, May, 2002   DOI   ScienceOn
12 K. Takeuchi, T. Tanaka, and T. Tanzawa, 'A multipage cell architecture for high-spped programming multilevel NAND flash memories,' IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp. 1228-1238, Aug., 1998   DOI   ScienceOn
13 S. Satoh et al., 'A novel channel boost capacitance (CBC) cell technology with low program disturbance suitable for fast programming 4 Gbit NAND flash memories,' Symposium on VLSI Technology Digest of Technical Papers, pp. 108-109, June, 1998
14 K. Suh et al., 'A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme,' IEEE Journal of Solid-State Circuits, Vol. 30, No. 11, pp. 1149-1156, Nov., 1995   DOI   ScienceOn
15 T. Tanzawa et al., 'A compact on-chip ECC for low cost Flash Memories,' IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, pp. 662-669, May, 1997   DOI   ScienceOn
16 B. Chen, X. Zhang, and Z. Wang, 'Error correction for multi-level NAND flash memory using Reed-Solomon codes,' IEEE Workshop on Signal Processing Systems, pp. 94-99, Oct., 2008
17 J. Lee et al., 'A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications,' IEEE Journal of Solid-State Circuits, Vol. 38, No. 11, pp. 1934-1942, Nov., 2003   DOI   ScienceOn
18 K. Takeuchi et al., 'A source-line programming scheme for low-voltage operation NAND flash memories,' IEEE Journal of Solid-State Circuits, Vol. 35, No. 5, pp. 672-681, May, 2000   DOI   ScienceOn
19 H. Lou, and C. Sundberg, 'Increasing storage capacity in multilevel memory cells by means of communications and signal processing techniques,' IEE Proceedings Circuits, Devices and Systems, Vol. 147, No. 4, pp. 229-236, Aug., 2000   DOI   ScienceOn