• Journal of IKEEE
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• v.18 no.3
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• pp.335-340
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• 2014

Recently, LED (Light Emitting Diode) becomes to be useful to apply for the lightening sources in electric systems and the lightening equipment since the power is less consumed with high efficiency, and the size and the weight of LED are small and light, respectively. The LED is controlled with constant current and SMPS (Switching Mode Power Supply). It is necessary for the LED manufacturer to secure the fundamental technology of designing LED chip, and to study the methodology to improve the power factor (PF) and to design the operational circuit for the development of LED to reduce the power loss in the application of LED lightening. The direct AC (Alternating Current) LED driving circuit, HV9910, is widely used in the industry field. In this paper, it is to evaluate the improved methodology for the power factor and efficiency through simulations when PFC (Power Factor Correction) and Noise Filter are added to HV9910.

• Journal of electromagnetic engineering and science
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• v.7 no.3
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• pp.103-108
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• 2007

In this paper, a low-power 2.4 GHz front-end for sensor network application (IEEE 802.15.4 LR-WPAN) is designed in a 0.18 um CMOS process. A power supply circuit with a novel temperature-compensation scheme is presented. The simulation and measurement results show that the front-end (LNA, Mixer) can achieve a voltage gain of 35.3 dB and a noise figure(NF) of 3.1 dB while consuming 5.04 mW (LNA: 2.16 mW, Mixer: 2.88 mW) of power at $27^{\circ}C$. The NF includes the loss of BALUN and BPF. The low-IF architecture is used. The voltage gain, noise figure and third-order intercept point (IIP3) variations over -45$^{\circ}C$ to 85$^{\circ}C$ are less than 0.2 dB, 0.25 dB and 1.5 dB, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.9-14
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• 2012

Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2335-2343
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• 2018

This paper proposes an optimal damping control algorithm of the DTI (Direct Two-level Inverter) to miniaturize and reduce the weight of auxiliary power supply for railway vehicles. The conventional auxiliary power supply for railway vehicles uses a DC-DC converter to maintain the inverter input power from the line voltage smoothly. The proposed topology does not use a DC-DC converter for reducing of manufacturing and maintenance costs. It also proposes a DTI topology removed damping resistors that generate ground signal noise in a certain period. At this time, a resonance phenomenon of DC-link voltage occurs due to variation of the inductive load, and a method of controlling the resonance phenomenon of DC-link voltage is required. In order to suppress the resonance phenomenon of the DC-link voltage, at a point before resonance occurs, this paper introduces an algorithm to suppress the resonance phenomenon of DC-link voltage by compensating the resonance component of the q axis voltage of the synchronous reference frame. The proposed algorithm verifies the effect through simulation and experiment.

• ETRI Journal
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• v.35 no.5
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• pp.819-826
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• 2013

A class-D audio amplifier for a digital hearing aid is described. The class-D amplifier operates with a pulse-code modulated (PCM) digital input and consists of an interpolation filter, a digital sigma-delta modulator (SDM), and an analog SDM, along with an H-bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class-D amplifier is implemented in a 0.13-${\mu}m$ CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class-D amplifier consumes 304 ${\mu}W$ from a 1.2-V power supply.

• Journal of Navigation and Port Research
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• v.35 no.9
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• pp.749-753
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• 2011

A leisure ship has a stand-alone type power system, and a generator is in use on this condition. But the generator cannot be operated in condition of leisure activity, ocean measurement and etc, because of environment and noise. Recently, renewable energy system is connected with power system of the leisure-ship for saving energy. The renewable energy system can not supply the stable power to leisure-ship because power generation changes according to weather condition. And most of the leisure ship is operated without methodical power management system. This study's purpose is to develop SPMS(Smart Power Management System) algorithm using the renewable energy (photovoltaic, wind power and etc.). The proposed algorithm is able to supply stable the power according to operation mode. Furthermore, the SPMS manages electric load (sailing and communication equipment, TV, fan, etc.) and reduces operating times of the generator. In this paper, the proposed algorithm is realized and executed by using LabVIEW. As a result, the hour for operating the generator is minimized.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.2 no.1
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• pp.11-15
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• 2009

In this study, we have developed the SMPS(Switched-mode power supply) power module for the medical kit. It is used the medical kit for improved supplying power better than the existing power module in performance, safety and reliability. The developed SMPS(Switched-mode power supply) is composed of the three fundamental electronic circuits, first one is for converting AC power to DC power, second one is for converting to high frequency, and the other is for absorbing noise frequency and preventing malfunction. It is possible for developed SMPS module to enlarge applications for PC, home appliances, switchboard as well as medical instruments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.1
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• pp.9-15
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• 2015

A CMOS band-pass delta-sigma modulator(BPDSM) and cascode class-E power amplifier have been developed CMOS for Class-S power amplifier applications. The BPDSM is operating at 1-GHz sampling frequency, which converts a 250-MHz sinusoidal signal to a pulse-width modulated digital signal without the quantization noise. The BPDSM shows a 25-dB SQNR(Signal to Quantization Noise Ratio) and consumes a power of 24 mW at an 1.2-V supply voltage. The class-E power amplifier exhibits an 18.1 dBm of the maximum output power with a 25% drain efficiency at a 3.3-V supply voltage. The BPDSM and class-E PA were fabricated in the Dongbu's 110-nm CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.255-265
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• 2012

This paper presents a 15-GHz multiphase rotary traveling-wave voltage-controlled oscillator (RTW VCO) where a shielded coplanar stripline (CPS) is exploited to provide better shielding protection and lower phase noise at a moderate cost of characteristic impedance and power consumption. Test chips were implemented in a standard 90-nm CMOS process, demonstrating the measured results of 2-GHz frequency tuning range, -11.3-dBm output power, -109.6-dBc/Hz phase noise at 1-MHz offset, and 2-ps RMS clock jitter at 15 GHz. The chip core occupies the area of $0.2mm^2$ and dissipates 12 mW from a single 1.2-V supply.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.283-286
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• 1999

A 2㎓, low noise, low power CMOS voltage-controlled oscillator (VCO) with an integrated LC resonator is presented. The design of VCO relies heavily on the on-chip spiral inductor. An optimized spiral inductor with Q-factor of nearly 8 is achieved and used for the VCO. The simulated result of phase noise is as low as -l14 ㏈c/Hz at an offset frequency of a 600KHz from a 2㎓ carrier frequency. The VCO is tuned with standard available junction capacitors, resulting in an about 400MHz tuning range (20%). Implemented in a five-metal 0.25${\mu}{\textrm}{m}$ standard CMOS process, the VCO consumes only 2㎽ from a single 2.5V supply. It occupies an active area of 620${\mu}{\textrm}{m}$$\times$720${\mu}{\textrm}{m}$.