Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
권호 표지
DOI QR코드

DOI QR Code

Interconnect Process Technology for High Power Delivery and Distribution

전력전달 및 분배 향상을 위한 Interconnect 공정 기술

  • 오경환 (서울과학기술대학교 글로벌융합산업공학과) ;
  • 마준성 (서울과학기술대학교 NID융합기술대학원) ;
  • 김성동 (서울과학기술대학교 기계시스템디자인공학과) ;
  • 김사라은경 (서울과학기술대학교 NID융합기술대학원)
  • Received : 2012.08.30
  • Accepted : 2012.09.11
  • Published : 2012.09.30
Download PDF
⟨ Previous Next ⟩

Abstract

Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.

전자 소자의 기술이 발달함에 따라 전력은 증가하고, 전압은 낮아지고, 입출력 범프 수가 증가하는 반면, 범프 피치는 크게 줄어들지 못하기 때문에 전력전달과 분배 문제는 점점 심각해지고 있다. 그동안 전력전달 문제를 해결하기 위해선 대부분 회로나 아키텍처 차원에서 에너지를 적게 소모하는 방법을 주로 연구해 왔으나, 최근 회로분야와 동시에 새로운 공정설계를 통해서 전력전달 및 분배를 높이고 발열 문제도 처리하는 interconnect 공정 기술이 중요시 되고 있다.

Keywords

References

  1. N. H. Khan, S. M. Alam and S. Hassoun, "Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies", IEEE Trans. VLSI systems, 19(4), 647 (2011). https://doi.org/10.1109/TVLSI.2009.2038165
  2. R. S. List, C. Webb and S. E. Kim, "3D Wafer stacking technology", Proc of AMC, 29 (2002).
  3. R. Plieninger, M. Dittes and K. Pressel, "Modern IC packaging trends and their reliability implications", Microelectron. Reliab., 1868 (2006).
  4. ITRS from http://www.itrs.net
  5. R. Bhooshan and B. P Rao, "Optimum IR Drop Models for Estimation of Metal Resource Requirements for Power Distribution Network", IFIP on VLSI, 292 (2007).
  6. M. Ketkar and E. Chiprout, "A microarchitecture based framework for pre- and post-silicon power delivery analysis", Microarchitecture, 42, 179 (2009).
  7. N. H. Khan, S. M. Alam and S. Hassoun, "System level comparison of power delivery design for 2D and 3D ICs 3D System Integration", IEEE 3DIC, 1 (2009).
  8. B. Amelifard and M. Pedram, "Optimal Selection of Voltage Regulator Modules in a Power Delivery Network", IEEE DAC, 168 (2007).
  9. M. Budnik and K. Roy, "A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies", IEEE Trans. VLSI Systems, 14(12), 1336 (2006).
  10. C. Wang, H. Cheng, C. Chiu, C. Hung and C. Kuo, "Through co-design to optimize power delivery distribution system using embedded discrete de-coupling capacitor", IEEE CPMT, 1 (2010).
  11. J. Sun, J. Q. Lu, D. Giuliano, T. P. Chow, R. J. Gutmann, "3D Power Delivery for Microprocessors and High-Performance ASICs", IEEE APEC, Feb. (2007).
  12. G. Schrom, P. Hazucha, J. Hahn, V. Kursun, D. Gardner, S. Narendra, T. Karnik and V. De, "Feasibility of Monolithic and 3D-Stacked DC-DC Converters for Microprocessors in 90 nm Technology Generation", ISLPED, 263 (2004).
  13. G. Huang, M. Bakir, A. Naeemi and H. Chen, J. Mei, "Power delivery for 3D chip stacks: Physical modeling and design implication", IEEE EPEP, 205 (2007).
  14. M. B. Healy and S. K. Lim, "Distributed TSV Topology for 3-D Power-Supply Networks", IEEE Trans. VLSI systems, 1 (2011).
  15. S. Kim, B. Martell, D. Ayers, S. List, P. Moon and S. Towle, "Thick metal layer integrated process flow to improve power delivery and mechanical buffering", US Patent No. 6, 977, 435 (2005).
  16. A. J. McNamara, Y. Joshi and Z. M. Zhang, "Characterization of nanostructured thermal interface materials", Int. J. Therm. Sci., In Press, Available online, November (2011).
  17. J. Xu and T. S. Fisher, "Enhancement of thermal interface materials with carbon nanotube arrays", Int. J. Heat Mass Transf., 49(9-10), 1658 (2006). https://doi.org/10.1016/j.ijheatmasstransfer.2005.09.039
  18. A. Hamdan, A. McLanahan, R. Richards and C. Richards, "Characterization of a liquid-metal microdroplet thermal interface material", Exp. Therm. Fluid Sci., 35(7), 1250 (2011). https://doi.org/10.1016/j.expthermflusci.2011.04.012
  19. S. N. Paisner, "Nanotechnology and mathematical methods for high-performance thermal interface materials", Global SMT & Packag., 36 (2008).
  20. H. Shin, H. Lee, J. Bang, S. Yoo, S. Jung and K. Kim, "Variation of Thermal Resistance of LED Module Embedded by Thermal Via", J. Microelectron. Packag. Soc., 17(4), 95 (2010).
  21. W. S. Lee, Y. W. Ko, C. S. Yoo, K. C. Kim and J. C. Park, "A Study on the Thermal Behavious of Via Design in the Ceramic Package", J. Microelectron. Packag. Soc., 10(1), 39 (2003).
  22. J. Darabi and K. Ekula, "Development of a chip-integrated micro cooling device", Microelectronics, 34(11), 1067 (2003). https://doi.org/10.1016/j.mejo.2003.09.010
  23. Y. M. Hung and Q. Seng, "Effects of geometric design on thermal performance of star-groove micro-heat pipes", Int. J. Heat Mass Transf., 54(5-6), 1198 (2011). https://doi.org/10.1016/j.ijheatmasstransfer.2010.09.070
  24. J. Vaes, W. Dehaene, E. Beyne and Y. Travaly, "Integration challenges of copper Through Silicon Via (TSV) metallization for 3D-stacked IC integration", Microelectron. Eng., 88(50, 745 (2011). https://doi.org/10.1016/j.mee.2010.06.026
  25. D. Kearney, T. Hilt and P. Pham, "A liquid cooling solution for temperature redistribution in 3D IC architectures", Microelectron., In Press, Available online, June (2011).
  26. F. Schindler-Saefkow, O. Wittler, D. May and B. Michel, "Thermal Management in a 3D PCB Package with Water Cooling", IEEE ESTC, 107 (2006).
  27. R. Hon, S. W. Ricky Lee, S. X. Zhang and C. K. Wong, "Multi-Stack Flip Chip 3D Packaging with Copper Plated Through-Silicon Vertical Interconnection", IEEE EPTC, 384 (2005).
  28. D. Sekar, C. King, B. Dang, T. Spencer, H. Thacker, P. Joseph, M. Bakir and J. Meindl, "A 3D-IC Technology with Integrated Microchannel Cooling", IEEE IITC, 13 (2008).
  29. C. R. King, Jr., J. Zaveri, M. S. Bakir and J. D. Meindl, "Electrical and Fluidic C4 Interconnections for Inter-layer Liquid Cooling of 3D ICs", IEEE ECTC, 1674 (2010).
  30. K. W. Yan, R. W. Johnson, R. Stapleto and K. Ghosh, "Double Bump Flip-Chip Assembly", IEEE Trans. EPM 29(2), 119 (2006).
  31. M. Topper, V. Glaw, P. Coskina, J. Auersperg, K. Samulewicz, M. Lange, C. Karduck, S. Fehlberg, O. Ehrmann and H. Reichl, "Wafer Level Package using Double Balls", Int. Sym. APM, 198 (2000).
  32. B. Keser, B. Yeung, J. White and T. Fang, "Encapsulated double- bump WL-CSP: design and reliability", IEEE ECTC 35 (2001).

Cited by

  1. Development of Cu CMP process for Cu-to-Cu wafer stacking vol.20, pp.4, 2013, https://doi.org/10.6117/kmeps.2013.20.4.081
  2. Characterization of flip chip bonded structure with Cu ABL power bumps vol.54, pp.8, 2014, https://doi.org/10.1016/j.microrel.2014.03.022