• The Journal of the Korea Contents Association
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• v.6 no.4
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• pp.1-10
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• 2006

In this paper, a broadband RF module is designed and tested for 2.4GHz band applications. The RF module is composed of a low noise amplifier (LNA) with a three stage amplifier, a single ended gate mixer, matching circuits, a hairpin line band pass filter and a Chebyshev low pass filter to convert the radio frequency (RF) into the intermediate frequency (IF). The LNA has a high gain and stability, and the single ended gate mixer has a high conversion gain and wide dynamic range. In the analysis of the broadband RF module, the composite harmonic balance technique is used to analyze the operating characteristics of an RF module circuit. The RF module has a 55.2dB conversion gain with a 1.54dB low noise figure, $-120{\sim}-60dBm$ wide RF power dynamic range, -60dBm low harmonic spectrum and a good isolation factor among the RF, IF, and local oscillator (LO) ports.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.2
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• pp.461-468
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• 2010

This paper presents a simple digital LCD backlight inverter using a single-chip microcontroller. The proposed inverter reduces the ignition voltage and eliminates the current spikes and hence improves the ignition behavior of the cold cathode fluorescent lamp(CCFL). Thus it increases the CCFL's life span. This is achieved by implementing a digital dimming control algorithm, that contains the soft-starting algorithm, all on a single-chip microcontroller. The inverter utilizes the full-bridge resonant circuit topology. The design example along with a simple analysis for the inverter is shown, and the experimental results of the designed prototype results in close agreement with the theoretical analysis and explanation. The overall system's power efficiency is approximately 85%. Compared with conventional inverters, the ignition voltage is reduced by around 30% without any lamp current spike occurring during the dimming control operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.397-401
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• 2005

In this paper, we have developed a frequency mixer which can be used as a microwave phase conjugator in the retrodirective array antenna. The retrodirective array, which can reflect the incident wave retrodirertively back to the source direction without any priori information, requires phase conjugators to achieve the phase change of 180 degrees for the incoming signal. frequency mixers can efficiently serve as phase conjugators. The circuit topology is of the 2-port structure to avoid the complexity of LO and Rf signal combination and matching circuits, using a pseudomorphic HEU device. The operating frequencies are 4.0 CHz, 2.01 CHz, and 1.99 CHz for LO, RF, and If signals, respectively. Conversion loss is measured to be -ldB and 1-dB compression point -l5 dBm at the LO power of -10 dBm.

• Journal of Advanced Navigation Technology
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• v.12 no.2
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• pp.122-131
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• 2008

In this paper, an S-band oscillator of the low phase noise property using miniaturized microstrip hairpin shaped ring resonator has been designed and implemented. The TACONIC's RF-35 substrate has a dielectric constant ${\varepsilon}_r$=3.5 a thickness h=20mil a copper thickness t=17 um and loss tangent $tan{\delta}$=0.0025. The designed and implemented 2.45 GHz oscillator shows low phase performance of -100.5 dBc/Hz a 100kHz offset. Output power 20.9 dBm at center frequency 2.45 GHz and harmonic suppression -32 dBc. The circuit was implemented with hybrid technique. But can be fully compatible with the RFIC's, MIC and MMIC due to its entirely planar structure.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.76-81
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• 2009

A novel design method of time-interleaved subranging ADC is presented. We use the bisection method to let only half of comparators in typical subranging ADC working in every clock cycle. Thus, we are able to reduce the number of comparators by half. It is possible to reduce the die size. An example of 8-bit time-interleaved subranging ADC operates at 40MHz sampling rate and 1.8V supply voltage is demonstrated. The power consumption of the proposed circuit is only 10mV with SPECTRE simulation. Compared with the typical subranging ADC, our bisection method is able to reduce up to 40% in die size.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.33-38
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• 2004

A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron $MOS({\nu}MOS)$ threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by ${\nu}MOS$ down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.2
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• pp.69-76
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• 2014

Multiple-input and multiple-output (MIMO) technique is used in many communication fields in order to increase the channel capacity. However, this MIMO system has difficulty of miniaturization of antenna size due to the multiple RF chains Also, multiple RF chain raises some problems which increase power consumption at RF circuit and degrade the system performance due to the interference between RF chains. Because of these reasons, beamspace MIMO (BS-MIMO) technique with only single RF chain was proposed for MIMO transmission. This BS-MIMO system basically uses electronically steerable parasitic array radiator (ESPAR) antenna. Existing ESPAR antenna has a 5-element structure. So, it is possible to do only $3{\times}3$ MIMO transmission. Therefore, in order to extend BS-MIMO dimension, extension of ESPAR antenna structure is essential. In this paper, we show that BS-MIMO dimension can be increased according to the extension of structure of the ESPAR antenna, as in the conventional MIMO techniques. For example, we show that it is possible to design the $7{\times}7$ BS-MIMO transmissions with the 13-element ESPAR antenna. Also, when the number of parasitic elements of ESPAR antenna increases by two elements, MIMO dimension is expanded by 1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.100-105
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• 2010

A multi-band low noise amplifier (LNA) is designed in 90 nm RF CMOS process for 3GPP LTE (3rd Generation Partner Project Long Term Evolution) applications. The designed multi-band LNA covers the eight frequency bands between 1.85 and 2.8 GHz. A tunable input matching circuit is realized by adopting a switched capacitor array at the LNA input stage for providing optimum performances across the wide operating band. Current steering technique is adopted for the gain control in three steps. The performances of the LNA are verified through post-layout simulations (PLS). The LNA consumes 17 mA at 1.2 V supply voltage. It shows a power gain of 26 at the normal gain mode, and provides much lower gains of 0 and -6.7 in the bypass-I and -II modes, respectively. It achieves a noise figure of 1.78 dB and a IIP3 of -12.8 dBm over the entire band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.10-17
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• 2011

As the data path of the processor widens and the depth of the pipeline deepens, the number of required registers increases. Consequently, careful attention must be paid to the design of clocked storage elements like latches and flipflops as they have a significant bearing on the overall performance of a synchronous VLSI circuit. As technology is also scaling down, noise immunity is becoming an important factor. In this paper, we present a new flipflop which has an improved noise immunity when compared to the hybrid latch flipflop and the conditional precharge flipflop. Simulation results in 65nm CMOS technology with 1.2V supply voltage are used to demonstrate the effectiveness of the proposed flipflop structure.