• Proceedings of the IEEK Conference
• /
• 2000.07b
• /
• pp.941-944
• /
• 2000

This paper proposes, for the first time, the design of class I pull-push power amplifier. With the new design, the output power is increased by four times when compared to conventional single-end class I connection amplifier with the same supply voltage. The performance of the proposed amplifier is verified by with a 100-kHz power amplifier constructed using general-purpose NPN transistors.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.604-607
• /
• 2008

In this study, p-channel silicon-oxide-nitride-oxide-silicon (SONOS) transistors are fabricated and characterized as an unit cell for NAND flash memory. The SONOS transistors are fabricated by $0.13{\mu}m$ low power standard logic process technology. The thicknesses of gate insulators are $20{\AA}$ for the tunnel oxide, $14{\AA}$ for the nitride layer, and $49{\AA}$ for the blocking oxide. The fabricated SONGS transistors show low programming voltage, fast erase speed, and relatively good retention and endurance.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.505-506
• /
• 2006

In this paper, the linearization technique for CMOS low-noise amplifier (LNA) using the derivative superposition method through the multiple gated transistors configuration is presented. LNA based on 0.13um RF CMOS process has been implemented with a modified cascode configuration using multiple gated common source transistors to fulfill a high linearity. Compared with a conventional cascode type LNA, the third order input intercept point (IIP3) per DC power consumption (IIP3/DC) is improved by 3.85 dB. The LNA achieved 2.5-dBm IIP3 with 13.4-dB gain, 3.6 dB NF at 2.4 GHz consuming 8.56 mA from a 1.5-V supply.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.30 no.8
• /
• pp.474-478
• /
• 2017

We report on thin-film transistors based on $TiO_x$ pre-annealed by femtosecond laser pulses. A 30-nm thick $TiO_x$ active channel layer was initially deposited by an ALD system. The $TiO_x$ semiconducting films were annealed by irradiation with a femtosecond laser (power: $3W/cm^2$) for 5, 25, and 50s. Atomic force microscopy images revealed that the surface of a $TiO_x$ film without femtosecond laser pre-annealing was relatively rough, while after annealing with femtosecond laser pulses, the surface of the $TiO_x$ films became smooth. With increasing radiation time, the surrounding gas atmosphere could have a larger impact on the $TiO_x$ surface; meanwhile, the thin-film roughness decreased. Thin-film transistors with $TiO_x$ active channels pre-annealed at 50s exhibited good transfer characteristics and an on-to-off current ratio of ${\sim}10^3$.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
• /
• v.11B no.3
• /
• pp.112-118
• /
• 2001

In the near future, the voltage of power system for passenger vehicle will be changed to 42V from existing 14V./ Because of increasing power and voltage ratings used in the vehicle the motor drive system has high switching dv/dt and it generates electromagnetic interference (EMI) To solve these problems multi-level inverter system may be used The feature of multi-level inverter is the output voltage to be synthesized from several levels of voltage Because of this feature high switching dv/dt and EMI can be reduced in the multi-level inverter system But as the number of level is increased manufacturing cost is getting expensive and system size is getting large. Because of these disadvantages the application of multi-level inverter has been restricted only to high power drives. The method to reduce manufacturing cost and system size is to integrate circuit of multi-level inverter into a few chips But isolated power supply and signal isolation circuit using transformer or opto-coupler for drive circuit are obstacles to implement the integrated circuit (IC) In this paper a drive circuit of 4-level inverter suitable for integration to hybrid or one chip is proposed In the proposed drive circuit DC link voltage is used directly as the power source of each gate drive circuit NPN transistors and PNP transistors are used to isolate to transfer the control signals. So the proposed drive circuit needs no transformers and opto-couplers for electrical isolation of drive circuit and is constructed only using components to be implemented on a silicon wafer With th e proposed drive circuit 4- level inverter system will be possible to be implemented through integrated circuit technology Using the proposed drive circuit 4- level inverter system is constructed and the validity and characteristics of the proposed drive circuit are proved through the experiments.

• Journal of electromagnetic engineering and science
• /
• v.14 no.3
• /
• pp.284-292
• /
• 2014

This paper presents a characteristic evaluation of commercial gallium nitride (GaN) transistors having two different gate-lengths of $0.4-{\mu}m$ and $0.25-{\mu}m$ in the design of a class-S power amplifier (PA). Class-S PA is operated by a random pulse-width input signal from band-pass delta-sigma modulation and has to deal with harmonics that consider quantization noise. Although a transistor having a short gate-length has an advantage of efficient operation at higher frequency for harmonics of the pulse signal, several problems can arise, such as the cost and export license of a $0.25-{\mu}m$ transistor. The possibility of using a $0.4-{\mu}m$ transistor on a class-S PA at 955 MHz is evaluated by comparing the frequency characteristics of GaN transistors having two different gate-lengths and extracting the intrinsic parameters as a shape of the simplified switch-based model. In addition, the effectiveness of the switch model is evaluated by currentmode class-D (CMCD) simulation. Finally, device characteristics are compared in terms of current-mode class-S PA. The analyses of the CMCD PA reveal that although the efficiency of $0.4-{\mu}m$ transistor decreases more as the operating frequency increases from 955 MHz to 3,500 MHz due to the efficiency limitation at the higher frequency region, it shows similar power and efficiency of 41.6 dBm and 49%, respectively, at 955 MHz when compared to the $0.25-{\mu}m$ transistor.

• Journal of IKEEE
• /
• v.17 no.3
• /
• pp.365-370
• /
• 2013

Power MOSFET is developed in power savings, high efficiency, small size, high reliability, fast switching, and low noise. Power MOSFET can be used in high-speed switching transistors devices. Recently attention given to the motor and the application of various technologies. Power MOSFET is a voltage-driven approach switching device and designed to handle on large power, power supplies, converters, motor controllers. In this paper, the 400 V Planar type, and the trench type for realization of low on-resistance are designed. Trench Gate Power MOSFET Vth : 3.25 V BV : 484 V Ron : 0.0395 Ohm has been optimized.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.3
• /
• pp.190-193
• /
• 2013

Power MOSFET and Power IGBT is develop in power savings, high efficiency, small size, high reliability, fast switching, low noise. Power MOSFET can be used high-speed switching transistors devices. Power MOSFET is devices the voltage-driven approach switching devices are design to handle on large power, power supplies, converters. In this paper, design the 80V MOSFET Planar Gate type, and design the Trench Gate type for realization of low on-resistance. For both structures, by comparing and analyzing the results of the simulation and characterization.

• Journal of Power Electronics
• /
• v.19 no.2
• /
• pp.443-453
• /
• 2019

As the core component of transmission systems, converters are very prone to failure. To improve the accuracy of fault diagnosis for wind power converters, a fault feature extraction method combined with a wavelet transform and compressed sensing theory is proposed. In addition, an improved AdaBoost-SVM is used to diagnose wind power converters. The three-phase output current signal is selected as the research object and is processed by the wavelet transform to reduce the signal noise. The wavelet approximation coefficients are dimensionality reduced to obtain measurement signals based on the theory of compressive sensing. A sparse vector is obtained by the orthogonal matching pursuit algorithm, and then the fault feature vector is extracted. The fault feature vectors are input to the improved AdaBoost-SVM classifier to realize fault diagnosis. Simulation results show that this method can effectively realize the fault diagnosis of the power transistors in converters and improve the precision of fault diagnosis.

• ETRI Journal
• /
• v.44 no.3
• /
• pp.491-503
• /
• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.