Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Improving the Linearity of CMOS Low Noise Amplifier Using Multiple Gated Transistors

Multiple Gated Transistors의 Derivative Superposition Method를 이용한 CMOS Low Noise Amplifier의 선형성 개선

  • Yang, Jin-Ho (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Kim, Hui-Jung (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Park, Chang-Joon (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Choi, Jin-Sung (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Yoon, Je-Hyung (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Kim, Bum-Man (Department of Electronic and Electrical Engineering Pohang University of Science and Technology)
  • 양진호 (포항공과대학교 전자전기공학과) ;
  • 김희중 (포항공과대학교 전자전기공학과) ;
  • 박창준 (포항공과대학교 전자전기공학과) ;
  • 최진성 (포항공과대학교 전자전기공학과) ;
  • 윤제형 (포항공과대학교 전자전기공학과) ;
  • 김범만 (포항공과대학교 전자전기공학과)
  • Published : 2006.06.21
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Abstract

In this paper, the linearization technique for CMOS low-noise amplifier (LNA) using the derivative superposition method through the multiple gated transistors configuration is presented. LNA based on 0.13um RF CMOS process has been implemented with a modified cascode configuration using multiple gated common source transistors to fulfill a high linearity. Compared with a conventional cascode type LNA, the third order input intercept point (IIP3) per DC power consumption (IIP3/DC) is improved by 3.85 dB. The LNA achieved 2.5-dBm IIP3 with 13.4-dB gain, 3.6 dB NF at 2.4 GHz consuming 8.56 mA from a 1.5-V supply.

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