• Journal of Electrical Engineering and Technology
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• 제9권4호
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• pp.1343-1348
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• 2014

The low frequency noise in Silicon Nanowire Field Effect Transistors is analyzed by characterizing the gate electrode dependence on various geometrical parameters. It shows that gate electrodes have a strong impact in the flicker noise of Silicon Nanowire Field effect transistors. Optimization of gate electrode was done by comparing different performance metrics such a DIBL, SS, $I_{on}/I_{off}$ and fringing capacitance using TCAD simulations. Molybdenum based gate electrode showed significant improvement in terms of high drive current, Low DIBL and high $I_{on}/I_{off}$. The noise power sepctral density is reduced by characterizing the device at higher frequencies. Silicon Nanowire with Si3N4 spacer decreases the drain current spectral density which interms reduces the fringing fields there by decreasing the flicker noise.

• 전력전자학회논문지
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• 제6권5호
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• pp.453-459
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• 2001

본 논문에서는 Two-transistor 포워드 컨버터에서 사용 가능한 기존의 소프트 스위칭 기법과 새로운 소프트 스위칭 기법의 손실 분석을 수행한다. 두 트랜지스터에서 발생하는 스너버 전류에 의한 트랜지스터 손실과 내부 커패시터에 의한 턴-온 손실을 유도하고, 각각의 트랜지스터에서 발생하는 전체 손실을 계산한다. 손실 계산을 통해 기존의 소프트 스위칭 기법에서는 두 트랜지스터에서 발생하는 손실이 상이함을 보이고, 새로운 소프트 스위칭 기법에서는 손실이 적으면서도 두 트랜지스터에서의 손실이 고르게 발생함을 알 수 있다. 그리하여 제안된 소프트 스위칭 스너버를 사용하여 고른 열분포와 향상된 신뢰도를 얻을 수 있음을 보인다.

• 대한전자공학회논문지
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• 제13권5호
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• pp.1-8
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• 1976

게이트의 길이가 2mm인 GaAb 금속반도체전계치과트랜지스터를 HP8545 자동회로망분석기에 의하여 주파수 1∼2GHz 사이에서 산란계수를 측정하였고, 산란계수의 도움으로 완전한 등가회로를 구현하였다. 본 논문에서는 50Ω의 높은 입출력 Impedance로 정합시키기 위하여 Microstrip을 사용하여 GaAs MESFET증폭기를 개발하였으며 전력이득이 8dB, 정재파비가 1.5보다 적은 결과를 얻었다. Microwave GaAs Metal Semiconductor Field effect Transistors (MESFET) with the gate-length of two micrometers are investigated. The scattering parameters of the transistors have been measured from 1GHz to 2GHz by Hp8545 Automatic network analyzer. From the measured data, an equivalent circuit is established which consists of an ntrinsic and. extrinsic transistor elements. In this paper, GaAb MESFET Amplifier is used in conjunction with conventional microstrip techniques to match into a 50 ohms high input/output impedances system. We found that Power gain is less than 8dB and VSWR is less than 1.5 in L-Band.

• 한국정보기술학회 영문논문지
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• 제8권2호
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• pp.59-67
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• 2018

The minimum power supply voltage of a typical bandgap current reference (BGCR) is limited by operating temperature and input common mode range (ICMR) of a feedback amplifier. A new BGCR using a bandgap voltage generator (BGVG) is proposed to minimize the effect of temperature, supply voltage, and process variation. The BGVG is designed with proportional to absolute temperature (PTAT) characteristic, and a feedback amplifier is designed with weak-inversion transistors for low voltage operation. It is verified with a $0.18-{\mu}m$ CMOS process with five corners for MOS transistors and three corners for BJTs. The proposed circuit is superior to other reported current references under temperature variation from $-40^{\circ}C$ to $120^{\circ}C$ and power supply variation from 1.2 V to 1.8 V. The total power consumption is $126{\mu}W$ under the conditions that the power supply voltage is 1.2 V, the output current is $10{\mu}A$, and the operating temperature is $20^{\circ}C$.

• Journal of Power Electronics
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• 제15권6호
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• pp.1489-1498
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• 2015

Gallium nitride (GaN)-based power switching devices, such as high-electron-mobility transistors (HEMT), provide significant performance improvements in terms of faster switching speed, zero reverse recovery, and lower on-state resistance compared with conventional silicon (Si) metal-oxide-semiconductor field-effect transistors (MOSFET). These benefits of GaN HEMTs further lead to low loss, high switching frequency, and high power density converters. Through simulation and experimentation, this research thoroughly contributes to the understanding of performance characterization including the efficiency, loss distribution, and thermal behavior of a 160-W GaN-based synchronous boost converter under various output voltage, load current, and switching frequency operations, as compared with the state-of-the-art Si technology. Original suggestions on design considerations to optimize the GaN converter performance are also provided.

• Journal of Power Electronics
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• 제16권3호
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• pp.883-893
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• 2016

This paper presents a comprehensive analysis of the spurious turn-on phenomena in phase-shifted full-bridge (PSFB) converters. The conventional analysis of the spurious turn-on phenomenon does not establish in the PSFB converter as realizing zero voltage switching (ZVS). Firstly, a circuit model is proposed taking into account the parasitic capacitors and inductors of the transistors, as well as the parasitic elements of the power circuit loop. Second, an exhaustive investigation into the impact of all these parasitic elements on the spurious turn-on is conducted. It has been found that the spurious turn-on phenomenon is mainly attributed to the parasitic inductors of the power circuit loop, while the parasitic inductors of the transistors have a weak impact on this phenomenon. In addition, the operation principle of the PSFB converter makes the leading and lagging legs have distinguished differences with respect to the spurious turn-on problems. Design guidelines are given based on the theoretical analysis. Finally, detailed simulation and experimental results obtained with a 1.5 kW PSFB converter are given to validate proposed analysis.

• ETRI Journal
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• 제43권4호
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• pp.717-727
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• 2021

In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current bestperforming techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.234-238
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a $0.25-{\mu}m$ standard CMOS Process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier, Total power dissipation is 7.5 mW.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.32-36
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• 2003

In this work, we have designed a fully integrated 2.4GHz LC-tuned voltage-controlled oscillator (VCO) with multiple tuning inputs for a 0.25-$\mu\textrm{m}$ standard CMOS process. The design of voltage-controlled oscillator is based on an LC-resonator with a spiral inductor of octagonal type and pMOS-varactors. Only two metal layer have been used in the designed inductor. The frequency tuning is achieved by using parallel pMOS transistors as varactors and back-gate tuned pMOS transistors in an active region. Coarse tuning is achieved by using 3-bit pMOS-varactors and fine tuning is performed by using back-gate tuned pMOS transistors in the active region. When 3-bit digital and analog inputs are applied to the designed circuits, voltage-controlled oscillator shows the tuning feature of frequency range between 2.3 GHz and 2.64 GHz. At the power supply voltage of 2.5 V, phase noise is -128dBc/Hz at 3MHz offset from the carrier. Total power dissipation is 7.5 mW.

• 센서학회지
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• 제33권3호
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• pp.152-157
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• 2024

In this study, we propose a novel 8T ternary SRAM that can process three logic values (0, 1, and 2) with only two additional transistors, compared with the conventional 6T binary SRAM. The circuit structure consists of positive and negative ternary inverters (PTI and NTI, respectively) with carbon-nanotube field-effect transistors, replacing conventional cross-coupled inverters. In logic '0' or '2,' the proposed SRAM cell operates the same way as conventional binary SRAM. For logic '1,' it works differently as storage nodes on each side retain voltages of V_DD/2 and V_DD, respectively, using the subthreshold current of two additional transistors. By applying the ternary system, the data capacity increases exponentially as the number of cells increases compared with the 6T binary SRAM, and the proposed design has an 18.87% data density improvement. In addition, the Synopsys HSPICE simulation validates the reduction in static power consumption by 71.4% in the array system. In addition, the static noise margins are above 222 mV, ensuring the stability of the cell operation when V_DD is set to 0.9 V.