• 한국전기전자재료학회논문지
• /
• 제29권2호
• /
• pp.79-83
• /
• 2016

This research was analyzed thermal characteristics that was appointed disadvantage when smart LED driver ICs was packaged and we applied extracted thermal characteristics for optimal layout design. We confirmed reliability of smart LED driver ICs package without additional heat sink. If the package is not heat sink, we are possible to minimize package. For extracting thermal loss due to overshoot current, we increased driver current by two and three times. As a result of experiment, we obtained 22 mW and 49.5 mW thermal loss. And we obtained optimal data of 350 mA driver current. It is important to distance between power MOSFET and driver ICs. If thhe distance was increased, the temperature of package was decreased. And so we obtained optimal data of 3.7 mm distance between power MOSFET and driver ICs. Finally, we fabricated real package and we analyzed the electrical characteristics. We obtained constant 35 V output voltage and 80% efficiency.

• ETRI Journal
• /
• 제44권3호
• /
• pp.491-503
• /
• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• 한국안전학회지
• /
• 제22권5호
• /
• pp.27-32
• /
• 2007

We investigated the damage of the TTL ICs which manufactured five different technologies by artificial microwave. The artificial microwave was rated at a microwave output from 0 to 1000W, at a frequency of 2.45GHz. The microwave power was extracted into a standard rectangular waveguide(WR-340) and TTL ICs were located into the waveguide. TTL ICs were damaged two types. One is breakdown which means no physical damage is done to the system and after a reset the system is going back into function. The other is destruction which means a physical damage of the system so that the system will not recover without a hardware repair. TTL SN74S08N and SN74ALS08N devices get a breakdown and destruction occurred but TTL SN74LS08N, SN74AS08N and 74F08N devices get a destruction occurred. Also destructed TTL ICs were removed their surface and a chip conditions were analyzed by SEM. The SEM analysis of the damaged devices showed onchipwire and bondwire destruction like melting due to thermal effect. The tested results expect to be applied to the fundamental data which interprets the combination mechanism of the semiconductors from artificial microwave environment.

• ETRI Journal
• /
• 제36권4호
• /
• pp.635-642
• /
• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• 한국전기전자재료학회논문지
• /
• 제15권12호
• /
• pp.1021-1026
• /
• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

• 대한전자공학회논문지SD
• /
• 제45권10호
• /
• pp.1-6
• /
• 2008

고전압 MOSFET에서 스냅백 이후의 유지 전압은 구동전압에 비해 매우 작아서 고전압 MOSFET이 파워 클램프로 바로 사용될 경우 래치업 문제를 일으킬 수 있다. 본 연구에서는 Drain-Extended PMOS를 이용하여 래치업 문제가 일어나지 않는 구조를 제안하였다. 제안된 구조에서는 래치업의 위험을 피하기 위해 소자가 스냅백이 일어나지 않는 영역으로 동작 영역을 제한하였다. $0.35\;{\mu}m$ 60V BCD(Bipolar-CMOS-DMOS) 공정을 사용하여 제작된 칩을 측정한 결과를 통해 제안된 기존의 gate-driven 구조의 LDMOS(Lateral Double-Diffused MOS)를 사용한 ESD 파워 클램프에 비해 500% 성능향상(강인성)이 있게 된 것을 알 수 있다.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2009년도 춘계학술대회
• /
• pp.845-848
• /
• 2009

전력용반도체(Power Management IC)는 전력의 변환이나 제어용으로 최적화되어 있는 전력장치용 반도체 소자로서 전자기기에 들어오는 전력을 그 전자기기에 맞게 변경하는 역할을 하며, 일반 반도체에 비해서 고내압화, 큰 전류화, 고주파수화 되어 있다. 전력용반도체는 전기가 쓰이는 제품에는 다 들어가며, 자동차, 공업제품, 컴퓨터와 주변기기, 통신, 가전제품, 모바일 기술, 대체 에너지 등에 대한 수요 증가가 시장의 성장을 촉진한다. 전력용반도체 개발을 통해 대일무역적자 해소 기여, 취약한 비메모리 산업의 육성을 통한 반도체산업의 균형발전, 신성장동력 창출을 통한 미래 경제발전을 도모할 수 있다. 본 고에서는 반도체 부문의 미래 유망품목인 전력용반도체의 필요성 및 중요성, 시장현황 및 전망을 중심으로 살펴보고 결론에서 정책적 시사점을 도출하고자 한다.

• 대한전자공학회논문지SD
• /
• 제46권1호
• /
• pp.1-6
• /
• 2009

고전압 소자에서 스냅백 이후의 유지 전압은 구동전압에 비해 매우 작아서 고전압 MOSFET이 ESD(ElecroStatic Discharge) 파워클램프로 바로 사용될 경우 래치업 문제를 일으킬 수 있다. 본 연구에서는 스택 바이폴라 소자를 이용하여 래치업 문제가 일어나지 않는 구조를 제안하였다. 제안된 구조에서는 유지 전압이 구동전압 보다 높으므로 래치업 문제가 발생하지 않으면서, 기존의 다이오드를 사용한 고전압 파워클램프에 비해 면적이 작으며, 내구성 측면에서 800% 성능향상이 있게 되었다. 제안된 구조는 $0.35{\mu}m$ 60V BCD(Bipolar-CMOS-DMOS) 공정을 사용하여 제작되었으며, TLP(Transmission Line Pulse) 장비로 웨이퍼-레벨 측정을 하였다.

• 디지털콘텐츠학회 논문지
• /
• 제19권6호
• /
• pp.1185-1195
• /
• 2018

산업제어시스템(ICS, Industrial Control System)은 산업 분야 제어 공정에 대한 감시와 제어를 수행하는 시스템을 말하며 수도, 전력, 가스 등 기반시설에서 응용되고 있다. 최근 ICS에 대해 Brutal Kangaroo, Emotional Simian, stuxnet 3.0 등 사이버공격이 지속적으로 증가하고 있고 이와 같은 보안위험은 인명피해나 막대한 금전적 손실을 초래한다. ICS에 대한 공격 방법 중 제어계층에 대한 공격은 제어명령을 조작해 현장장치계층의 장치를 오작동하게 하는 것이다. 따라서, 본 논문에서는 이에 대한 대응으로 산업제어시스템에서 제어계층과 현장장치 계층사이에 SDN을 적용해서 제어명령의 정상 여부를 판별하는 메커니즘을 제안하고 가상의 제어시스템을 구성해 시뮬레이션 결과를 소개한다.

• Nuclear Engineering and Technology
• /
• 제52권5호
• /
• pp.995-1001
• /
• 2020

With the development of digital instrumentation and control (I&C) devices, cyber security at nuclear power plants (NPPs) has become a hot issue. The Stuxnet, which destroyed Iran's uranium enrichment facility in 2010, suggests that NPPs could even lead to an accident involving the release of radioactive materials cyber-attacks. However, cyber security research on industrial control systems (ICSs) and supervisory control and data acquisition (SCADA) systems is relatively inadequate compared to information technology (IT) and further it is difficult to study cyber-attack taxonomy for NPPs considering the characteristics of ICSs. The advanced research of cyber-attack taxonomy does not reflect the architectural and inherent characteristics of NPPs and lacks a systematic countermeasure strategy. Therefore, it is necessary to more systematically check the consistency of operators and regulators related to cyber security, as in regulatory guide 5.71 (RG.5.71) and regulatory standard 015 (RS.015). For this reason, this paper attempts to suggest a template for cyber-attack taxonomy based on the characteristics of NPPs and exemplifies a specific cyber-attack case in the template. In addition, this paper proposes a systematic countermeasure strategy by matching the countermeasure with critical digital assets (CDAs). The cyber-attack cases investigated using the proposed cyber-attack taxonomy can be used as data for evaluation and validation of cyber security conformance for digital devices to be applied, and as effective prevention and mitigation for cyber-attacks of NPPs.