• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.7 s.349
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• pp.29-37
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• 2006

This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize the resonance effects, the resonance frequency of the circuit is accurately estimated in an analytical manner. Thereby, a decoupling capacitor size to suppress the resonance for a suitable circuit operation is accurately determined by using the estimated resonance frequency. The developed novel design methodology is verified by using $0.18{\mu}m$ process-based-HSPICE simulation.

• Journal of Power Electronics
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• v.13 no.3
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• pp.400-408
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• 2013

This paper presents a discrete state-space controller using state feedback control and feed-forward decoupling to provide a desirable control bandwidth and control stability for dynamic voltage restorers (DVR). The paper initially discusses three typical applications of a DVR. The load-side capacitor DVR topology is preferred because of its better filtering capability. The proposed DVR controller offers almost full controllability because of the multi-feedback of state variables, including one-beat delay feedback. Feed-forward decoupling is usually employed to prevent disturbances of the load current and source voltage. Directly obtaining the feed-forward paths of the load current and source voltage in the discrete domain is a complicated process. Fortunately, the full feed-forward decoupling strategy can be easily applied to the discrete state-space controller by means of continuous transformation. Simulation and experimental results from a digital signal processor-based system are included to support theoretical analysis.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.324-327
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• 2002

For the characterization of arbitrary shaped printed circuit board, lossy transmission line grid model based on SPICE netlist and analytical plane model based on the segmentation method are proposed in this paper. Two methods are compared with an arbitrary shaped power/ground plane. Furthermore, design considerations for the complete power distribution network structure are discussed to ensure the maximum value of the PDN impedance is low enough across the desired frequency range and to guide decoupling capacitor selection.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1456-1467
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• 2015

This paper presents a novel close-loop control scheme based on small signal modeling and weighted composite voltage feedback for a three-phase input and single-phase output Matrix Converter (3-1MC). A small non-polar capacitor is employed as the decoupling unit. The composite voltage weighted by the load voltage and the decoupling unit voltage is used as the feedback value for the voltage controller. Together with the current loop, the dual-loop control is implemented in the 3-1MC. In this paper, the weighted composite voltage expression is derived based on the sinusoidal pulse-width modulation (SPWM) strategy. The switch functions of the 3-1MC are deduced, and the average signal model and small signal model are built. Furthermore, the stability and dynamic performance of the 3-1MC are studied, and simulation and experiment studies are executed. The results show that the control method is effective and feasible. They also show that the design is reasonable and that the operating performance of the 3-1MC is good.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.340-343
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• 2002

Electromagnetic(EM) radiation problems and their possible solutions are addressed in this paper for the split power plane of high-speed digital systems. Stitching and decoupling capacitors are proved to be very effective fur reducing signal noise, ground bounce as well as electromagnetic radiation from the split power plane. Simulations based on 3D-Finite Difference Time Domain (FDTD) method are utilized for the analysis of practical high frequency multi-layered PC main board

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.4
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• pp.148-155
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• 1986

This paper presents a new decoupled power system state estimation method. The decoupling is achieved via simple linear transformation on power measurements in contrast with the modified fast decoupled state estimation method which assumes decoupling by direct negligence of the off-diagonal blocks of the observation functions. The new estimation method is compared with the modified decoupled state estimation method against IEEE-14 bus model power system and 25 bus model power system in several system conditions. It is observed that the proposed method shows better convergence performance and filtering performance than a modified fast decoupled state estimation.

• Journal of electromagnetic engineering and science
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• v.2 no.2
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• pp.75-80
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• 2002

Signal integrity problems and their possible solutions are addressed in this paper for split power plane of high-speed digital systems. Stitching and decoupling capacitors are proved to be very effective for reducing signal noise, ground bounce as well as electromagnetic radiation from the split power plane. Simulations based on 3D-Finite Difference Time Domain (FDTD) method are utilized for the analysis of practical high frequency multi-layered PC main board.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.419-420
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• 2015

In this paper, a low-cost single-phase PWM rectifier with small DC-link capacitors is proposed, where a buck-boost converter with a low power rating is added at the DC link. By controlling the auxiliary circuit so as to absorb the voltage ripple in the DC link, the second-order voltage ripple in DC-link capacitor can be reduced significantly. Therefore, a small film capacitor can be utilized to replace the bulky electrolytic capacitors. The simulation results are shown to verify the validity of the proposed method.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.421-422
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• 2015

Nowadays, bidirectional DC-DC converters are becoming more into picture for different applications especially electric vehicles. There are many bidirectional DC-DC converters topologies; however, voltage-fed Dual Half-Bridge (DHB) topology has less number of switches as compared to other isolated bidirectional DC-DC converters. Furthermore, voltage fed DHB has galvanic isolation, high power density, reduced size, high efficiency and hence cost effective. Electrolytic capacitors always have problem regarding size and reliability in DC-AC single phase inverters. Therefore, voltage-fed DHB converter is proposed for the purpose of power decoupling to replace electrolytic capacitor by film capacitors. A new control strategy has been developed for 120Hz ripple rejection, and it was verified by simulation.