• Journal of Korea Society of Industrial Information Systems
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• v.23 no.3
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• pp.25-34
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• 2018

This paper presents a heating source of carbon nanofibers for the efficiency and the drying performance of laundry dryer, and focuses on the applicability-evaluation of its source. To design the proposed heating module, experiments were conducted in terms of surface temperature and surface temperature distribution characteristics of carbon nanofiber lamps. The surface temperature of the lamps increased linearly with increment of a current to flow a lamp and revealing the increasing pattern as the length of the ramps is shorter. The proposed heating source was evaluated based on drying efficiency, moisture evaporation rate at laundry, and internal temperature of a drum during drying process. The drying efficiency satisfied a 45% which is specified in KS C 9319. The moisture evaporation rate and the internal temperature of the drum were respectively 98.88% and $61.1^{\circ}C$, which are similar to that of S's company dryer. From the evaluation and actual drying test results, the proposed carbon nanofiber lamp heating module is considered to be applicable as a heat source for laundry dryer in terms of drying efficiency and drying performance. it is possible to obtain a heat source at a high temperature, an excellent calorific value, an improvement in drying performance, and an effect of sterilizing laundry due to the emission of far-infrared rays. In addition to the applicability, the difference of the drying efficiency between the dryers was analyzed in detail based on the power consumption of the heat sources.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.10
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• pp.1117-1125
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• 2007

In this paper, a study has been performed on the design of small loop probe and analysis of induced electromagnetic wave signal from a smartcard for contactless cryptographic analysis. Probes for cryptographic analysis are different from conventional EM probes, because the purpose of proposed probe is to obtain the information for secret key analysis of cryptographic system. The waveform of induced voltage on probe must be very close to radiated waveform from IC chip on smartcard because electromagnetic attack makes an attempt to analyze the radiated waveform from smartcard. In order to obtain secret key information, we need to study about cryptographic analysis using electromagnetic waves, an approximate model of source, characteristic of probe for cryptographic analysis, measurement of electromagnetic waves and calibration of probes. We measured power consumption signal on a smartcard chip and electromagnetic wave signal using proposed probe and compared with two signals of EMA point of view. We verified experimently the suitability of the proposed small loop probe for contactless cryptographic analysis by applying ARIA algorithm.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.1
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• pp.69-76
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• 2017

Bluetooth Low Energy (BLE), also known as Bluetooth Smart, has ultra-low power consumption; in fact, BLE-enabled devices can run on a single coin cell battery for several years. In addition, BLE can estimate the approximate distance between two devices using the Received Signal Strength Indication (RSSI) feature, enabling relatively precise navigation in indoor and small outdoor areas where GPS is not an option. In this paper, an experimental setup is presented in which BLE is used for navigation within a small outdoor area. BLE-based beacons are installed in fixed positions, which periodically transmit a universally unique identifier (UUID). A smart device receives the UUID and sends it to a database server using cellular or Wi-Fi technology. The server returns fixed position information corresponding to the received UUID codes, and the smart device uses that information to compute its current position based on relative signal strengths, and display it on a map. These results demonstrate the successful application of BLE technology for navigation in small outdoor areas. This system can be implemented for indoor navigation as well.

• Journal of the Korea Society of Computer and Information
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• v.16 no.10
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• pp.1-10
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• 2011

There are the large overhead of block erase and page write operations in NAND flash memory, though it has low power consumption, cheap prices and a large storage. Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, so rewriting operation require after erase operation. it cause performance decrease of NAND flash memory. Using SRAM buffer in traditional NAND flash memory, it can not only reduce effective write operation but also guarantee fast memory access time. In this paper, we proposed the small SRAM buffer management system for reducing overhead of NAND flash memory, that is, erase and write operations. The proposed buffer system in a NAND flash memory consists of two parts, i.e., a fully associative temporal buffer with the small fetching block size and a fully associative spatial buffer with the large fetching block size. The temporal buffer have small fetching blocks that referenced from spatial buffer. When it happen write operations or erase operations in NAND flash memory, the related fetching blocks in temporal buffer include a page or a block are written in NAND flash memory at the same time. The writing and erasing counts in NAND flash memory can be reduced. According to the simulation results, although we have high miss ratios, write and erase operations can be reduced approximatively 58% and 83% respectively. Also the average memory access times are improved about 84% compared with the fully associative buffer with two sizes.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.3
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• pp.96-101
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• 2015

This paper describes a design and implementation of the NFC bridge chip which performs interface between kinds of devices and mobile phones including NFC controller through NFC communication. The NFC bridge chip consists of the digital part and the analog part which are based on NFC Forum standard. Therefore the chip treats RF signals and then transforms the signal to digital data, so it can interface kinds of devices with the digital data. Especially the chip is able to detect RF signals and then wake up the host processor of a device. The wakeup function dramatically decreases the power consumption of the device. The carrier frequency is 13.56MHz, and the data rate is up to 424kbps. The chip has been fabricated with SMIC 180nm mixed-mode technology. Additionally an NFC bridge chip application to the blood glucose measurement system is described for an application example.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.8
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• pp.74-85
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• 2015

PCI Express is a well-known and widely used de-facto system bus standard for connecting among a processor and IO devices. PCI Express is originated from old PCI standard, and its most of applications are limited to be used within a PC or server system. But, because of its fast speed, low power consumption, and good protocol efficiency, it is considered as one of a good candidate for an alternate system interconnect for many years. In this paper, we present design, implementation and early evaluation of an alternate system interconnect by utilizing PCI Express. The developed alternate system interconnect using PCI Express (named PCIeLINK) utilizes non-transparent bridging (NTB) technic which generally used in fail-over system in PCI and PCI Express. By using NTB technic, PCI Express device can be extended to outside of a system without electrical and logical problems arising during system boot and enumeration. To build up an alternate system interconnect, we designed and implemented a network interface card having multiple PCI Express ${\times}4$ connections (theoretically 20 Gbps) and tested, The early test results revealed that an ${\times}4$ port in the card showed 8.6 Gbps peak performance for bulk transmission and 5.1 Gbps peak for normal TCP/IP transfer.

• Information Systems Review
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• v.13 no.1
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• pp.75-96
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• 2011

This research uses coolhunting to predict the future trend of e-Commerce industry. Coolhunting is a method to take Cool Trends which are the future trend through social network analysis for discovering the trendsetter and its collective intelligence. Coolhunting is generally carried out by social network analysis while this research uses NodeXL of social network analysis tools. We designed industrial network research model for relation among e-Commerce corporation, product, the types of customer service and customer service employee to discover the Cool Trends of e-Commerce industry. According to the result of this research, e-Commerce industrial network was being changed from chaos to collective intelligence form. As a analysis result for network influences, we found that Cool Trends of e-Commerce industry invigorate social commerce industry through the collective intelligence focusing intelligence VIP, Excellence, grade of Administrating for women customers(trendsetter) and it promotes semantic consumption from customers and purchasing power will be concentrated on cosmetic, beauty, perfume product categories in social commerce. We propose the strategic direction for e-Commerce corporation and hope that domestic e-Commerce corporation continues to grow and high-quality services are provided for customers.

• Journal of Internet Computing and Services
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• v.12 no.6
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• pp.73-82
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• 2011

The location-based service is emerging again to the public attention. The location recognition environment up-to-now has been studied with its focus only on a person, an object or a moving object. However, this study proposes a location recognition model that serves to recognize and track, in real time, multiple passengers in a moving vehicle. Identifying the locations of passengers can be classified into two classes: one is to use the high price terminal with GPS function, and the other is to use the economic price compact terminal without GPS function. Our model enables the simple compact terminal to provide effective location recognition under the on-boarding situation by transmitting messages through an interface device and sensor networks for a vehicle equipped with GPS. This technology reduces transmission traffic after detecting the condition of a vehicle (being parked or running), because it does not require transmission/receiving of information on the locations of passengers who are confined in a vehicle when the vehicle is running. Also it extends battery life by saving power consumption of the compact terminal. Hence, we carried out experiments to verify its serviceability by materializing the efficient tracking system for passengers with the detection algorithm of a stopping vehicle proposed in this study. Moreover, about 200 experiments using the system designed with this technology proved successful recognition on on-boarding and alighting of passengers with the maximum transmission distance of 12 km. In addition to this, the running recognition tests showed the test with the detection algorithm of a stopping vehicle has reduced transmission traffic by 41.6% compared to the algorithm without our model.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.