• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.6B
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• pp.1114-1119
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• 2000

In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(fo=100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPICE simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.

• Proceedings of the KSME Conference
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• 2001.11a
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• pp.679-685
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• 2001

In this paper, the dynamic response of the pantograph system that supplies electrical power to a high-speed rail vehicle were investigated. The analysis of the catenary based on the Finite Element Method (FEM) is executed to develop a pantograph fits well in high-speed focused on the dynamic characteristic analysis of the pantograph system. By simulation of the pantograph-catenary system, the static deflection of the catenary, the stiffness variation in contact lines, the dynamic response of the catenary undergoing constant moving load and the contact force analysis were executed. In order to consider the design variables that effects on the dynamic characteristic of the pantograph system performed the dynamic sensitivity analysis. From the pantograph-catenary analysis, the design parameters of a pantograph could be improved. From the results of the sensitivity analysis, a pantograph with improved parameters is suitable for a high-speed rail vehicle from the design-parameter analysis.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.9
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• pp.36-43
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• 2013

The prevalence of electronic devices in our modern life is accompanied with the generation of harmonics caused by the nonlinear characteristic load. Especially, the employment of LED have brought the rapid use of SMPS. SMPS is used for supplying the constant DC electric power to the LED display board, but it has a big problem which gives birth of harmonics causing by its high-speed switching. measurement HIOKI 3196 equipment to solve these harmonics were measured. In this study, we are LED Display Board Load Measuring the impedance response with $X_L$ changes for removing harmonics in the measured. And we adopted the suitable passive filter by the impedance response characteristic obtained in the $X_L$ variation experiments. We are trying to deeply the application of passive harmonic filter characteristics that generation in the LED Display Board through EDSA LED simulation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.60-68
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• 2000

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.1
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• pp.91-102
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• 2013

This paper proposes the improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source DC-DC converter (Improved LCCT ZSDC) which can generate the bipolar output voltages according to duty ratio D. The proposed converter has the characteristic and structure of Quasi Z-source DC-DC converter(Quasi ZSDC) and conventional LCCT Z-source DC-DC converter(LCCT ZSDC). To confirm the validity of the proposed method, PSIM simulation and a DSP based experiment were performed for each converter. In case which the input DC voltage is 70V, the bipolar output DC voltage of positive 90V and negative 50V could generate. Also, as comparison result of the capacitor voltage ripple in Z-network and the input current under the same condition for each converter, the voltage stress and the capacitor voltage in Z-network of the proposed method were lower compared with the conventional methods. Finally, the efficiency for each method was investigated according to load variation and duty ratio D.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.75-80
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• 2005

In this paper, 2-stage power amplifier has been designed for 5.8GHz wireless LAN application. The power amplifier PldB output power has 21.6dBm at 5.8GHz frequency. Also the power amplifier shows 17.6dB gain and -17.8dB input return loss at 5.725GHz to 5.825GHz. The OFDM modulation and transmission block have been modeled in order to analyse the relationship between the power amplifier distortion and output ACPR for the IEEE 802.11a wireless LAN. The nonlinear characteristic of the power amplifier has been modeled as AM-to-AM and AM-to-PM using the behavioral model, and the output spectrum is analysed with the phase distortion variation. Also, amplifier back-off value from PldB to satisfy the required IEEE 802.11a standard spectrum mask has been simulated with phase distortion, and the simulation data have been compared to the measurement result collected by using the pre-distortion technique.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.6
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• pp.1460-1464
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• 2010

In the paper, the breakdown voltage of Trench D-MOSFET have been analyzed by using MircoTec. The technology for characteristic analysis of device for high integration is changing rapidly. Therefore to understand characteristics of high-integrated device by computer simulation and fabricate the device having such characteristics became one of very important subjects. A Trench MOSFET is the most preferred power device for high voltage power applications. The oxide thickness and doping concentration in Trench MOSFET determines breakdown voltage and extensively influences on high voltage. We have investigated the breakdown voltage characteristics according to variation of doping concentration from $10^{15}cm^{-3}$ to $10^{17}cm^{-3}$ in this study. We have also investigated the breakdown voltage characteristics according to variation of oxide thickness and junction depth.

• Proceedings of the KSME Conference
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• 2001.06b
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• pp.571-577
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• 2001

In this paper, the dynamic response of the pantograph system that supplies electrical power to a high-speed rail vehicle were investigated. The analyses of the catenary based on the Finite Element Method (FEM) is executed to develop a pantograph fits well in high-speed focused on the dynamic characteristic analysis of the pantograph system. By simulation of the pantograph-catenary system, the static deflection of the catenary, the stiffness variation in contact lines, the dynamic response of the catenary undergoing constant moving load and the contact force analysis were executed. By the pantograph-catenary analysis, the design parameters of a pantograph could be optimized. For more improving the dynamic characteristics of the pantograph, the active-pantograph was investigated by controlling a contact force. The active pantograph showed the better performance compared to the parameter-optimized. However, the parameter-optimized pantograph would be acceptable for a high-speed rail vehicle through the design-parameter analysis.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.39-44
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• 2005

The OFDM modulation and transmission block have been modeled in order to analyse the relationship between the 2.4GHz power amplifier distortion and output ACPR for the IEEE 802.11g wireless LAN. The nonlinear characteristic of the power amplifier has been modeled as AM-to-AM and AM-to-PM using the behavioral model, and the output spectrum is analysed with the phase distortion variation. Also, amplifier back-off value from P1dB to satisfy the required IEEE 802.11g standard spectrum mask s been simulated with modeled phase distortion, and the simulation data have been compared to the measured result by using the pre-distortion technique.