• 제목/요약/키워드: Power Amp

검색결과 202건 처리시간 0.026초

유무선 통신용 MEMS 온습도 네트워크 센서 (MEM Temperature and Humidity Network Sensor for Wire and Wireless Network)

  • 정우철;차부상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.360-361
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    • 2006
  • This paper describes a wire and wireless network sensor for temperature and humidity measurements. The network sensor comprises PLC(Power Line Communication) and RF transmitter(433MHz) for acquiring an internal (on-board) sensor signal, and measured data is transmitted to a main processing unit. The network sensor module is consist of MEMS sensor, 10-bit A/D converter, pre-amp., gain-amp., ADUC812 one chip processor and PLC/RF transmitting unit. The temperature and humidity sensor is based on MEMS piezoelectric membrane structure and is implemented by using dual function sensor for smart home and smart building.

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Power Amp.용 3KW급 ZVT PFC 개발 (A Study on the ZVT PFC for Using 3[KW] Power Amplifier)

  • 이성룡;정채규;김성우;고성훈
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 B
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    • pp.1306-1308
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    • 2000
  • A new ZVT PFC for using 3[KW] power amplifier is proposed. Generally, the single phase diode rectifier has been widely used in the SMPS of the conventional power amplifier. But this rectifier has occurred some problems which are the input power factor and current harmonics. To solve the above problems, in this paper, two topology is adopted. The one is the boost type PFC for improving the input power factor. The other is the ZVT resonant circuit for reducing the switching loss and stress. In this paper, the proposed topology is analyze designed to built the ZVT PFC for using 3[KW] power amplifier. In order to verify the circuit va finally, the PSPICE simulation and experiment results are presented.

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저전력 8비트 10MS/s 파이프라인 ADC 설계 (A Design of 8bit 10MS/s Low Power Pipelined ADC)

  • 배성훈;임신일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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    • pp.606-608
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    • 2006
  • This paper describes a 8bit 10MS/s low power pipelined analog-to-digital converter(ADC). To reduce power consumption in proposed ADC, a high gain op-amp that consumes large power in MDAC(multiplying DAC) of conventional pipelined ADC is replaced with simple comparator and current sources. Moreover, differential charge transfer amplifier technique with latch in the sub-ADC reduces the power consumption to less than half compared with the conventional sub-ADC which use high speed comparator. The proposed ADC shows the power consumption of 1.8mW at supply voltage of 1.8V. This proposed ADC is suitable to apply to the portable display device. The circuit was implemented with 0.18um CMOS technology and the core size of circuit is 2.5mm${\times}$1mm.

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Design of Low Power TFT-LCD Data Driver and Analog Buffer for Mobile Devices

  • Kim, Joon-Hoon;Kim, Seong-Joong;Shim, Hyun-Sook;Kwon, Oh-Kyong
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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    • pp.686-689
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    • 2003
  • This paper describes two kind of new concept for low power consumption for small area TFT-LCDs. First, the proposed analog buffer could reduce the static current by adopting new scheme. Second, new data driver structure reduced DC power consumption by reducing the number of operational amplifier (op-amp). As simulation results of Hspice, the quiescent current of proposed analog buffer is less than $0.8{\mu}A$ and the DC power consumption is reduced about $40{\sim}50%$ compared with conventional ones.

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8-bit 60Ms/s 파이프라인 아날로그 디지털 변환기 (A Pipelined 60Ms/s 8-bit Analog to Digital Converter)

  • 조은상;정강민
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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    • pp.253-256
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    • 2001
  • This paper introduces the design of high-speed analog- to-digital converter for high-definition TV, camcorders, portable equipments and implemented in a 0.65${\mu}{\textrm}{m}$ CMOS technology. Key circuits developed for low power and high speed A/D converter are a dynamic comparator that consumes no static power, a source follower buffered op amp that achives wide bandwidth using large input devices. The converter achieves low power dissipation of 40-mW at 3.3-V power supply. Measured performance includes 0.53 LSB of INL and 0.48 LSB of DNL while sampling at 60MHz.

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전력증폭기의 비선형 특성과 Memory Effect를 보상하기 위한 Look-up Table 방식의 Digital Pre-distorter (Look-up Table type Digital Pre-distorter for Linearization Power Amplifier with Non-linearity and Memory Effect)

  • 최홍민;김왕래;유재우;안광은
    • 한국정보통신설비학회:학술대회논문집
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    • 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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    • pp.218-222
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    • 2008
  • RF power amplifier requires linearization in order to reduce adjacent channel interference. And most of the existing linearization algorithms assume that a PA has memory-less nonlinearity. But for the wider bandwidth signal, the memory effect of PA cannot be ignored. This paper investigates digital pre-distortion by use of a memory polynomial model which compensates for amplifier nonlinearity and memory effect. The look-up table based implementation scheme is used to reduce the computational complexity of the pre-distortion block. The linearization performance is demonstrated on wideband CDMA signal and class AB high power amplifier.

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단일 역률 달성을 위한 Boost Converter용 PFC IC 설계 (Design of Boost Converter PFC IC for Unity Power Factor Achievement)

  • 전인선;김형우;김기현;서길수;조효문;이종화
    • 대한전자공학회논문지SD
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    • 제47권2호
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    • pp.60-67
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    • 2010
  • 본 논문에서는 입력 전류를 정현파가 되도록 제어하기 위하여 boost 인덕터 전류의 평균값이 정현파 모양을 따라가도록 하는 평균전류 제어 방식의 PFC IC를 설계하였다. 설계된 IC는 EMI 규격에 적합하도록 75kHz의 고정주파수를 가지고 고속 제어를 위해 넓은 대역폭을 갖도록 오차 증폭기 및 전류 증폭기에 RC 보상 루프를 구성하였다. 또한 시스템 내부의 오실레이터를 이용해 구형파와 삼각파를 발생시켜 역률제어에 적합한 신호를 생성하고, UVLO, OVP, OCP, TSD의 회로를 추가하여 시스템이 안정적으로 동작이 되도록 하였다. 설계된 IC는 $1{\mu}m$ High Voltage(20V) CMOS 공정을 이용하였고, 역률보정기능과 각종 보호 회로를 검증하기 위해 Cadence의 Spectre simulator를 이용하였다.

성능이 향상된 Stack Monitoring System의 설계 (Design of Stack Monitoring System with Improved Performance)

  • 장경욱;이주현;이승원;이승호
    • 전기전자학회논문지
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    • 제20권3호
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    • pp.299-302
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    • 2016
  • 본 논문에서는 성능이 향상된 Stack Monitoring System을 설계한다. Stack Monitoring System의 증폭기(AMP)에 들어오는 펄스성 잡음을 차단하기 위하여, 차폐 및 전원부 임피던스를 낮추고 전원회로를 분리하여 노이즈를 차단한다. 신틸레이션 검출기 특성을 최대한 장치에 매칭하기 위한 가변 고전압, 이득(Gain), 상쇄(Offset), 한계(Threshold) 등을 설정 할 수 있는 제어부를 설계한다. 또한 300 ~ 1,500V의 가변 고전압 전원회로를 구성하여 다양한 신틸레이션 검출기에 적용가능 한 가변 전압 공급 장치를 설계한다. 성능이 향상된 Stack Monitoring System은 다종의 신틸레이션 검출기가 각각의 특성을 고려하여 동작하게 함으로서 효율적이고 높은 신뢰성을 보장한다. 개발된 Stack Monitoring System의 측정 불확도에 대하여 공인 시험기관의 장비를 사용하여 실험한 결과 우수한 성능을 나타내었다.

육미지황탕(六味地黃湯)이 생리활성지표(生理活性指標)와 임파구세포수(淋巴球細胞數)에 미치는 영향(影響) (Correlative Effects of Yookmijihwangtang(六味地黃湯) on the T helper cell count, Blood cAMP, Testosterone and Cortisol)

  • 김영권;류봉하;박동원;류기원
    • 대한한방종양학회지
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    • 제4권1호
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    • pp.89-110
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    • 1998
  • Yookmijihwangtang has been widely used oriental herb prescriptions, which is healing some discuss that come from insufficiency of innate essence and deficiency of kidney Ki. The meaning of healing discusses tonification of insufficient innate essence and insufficient kidney Ki can be regarded as reinforcement of wholely power of keeping homeostasis, that is correlated with immuno-responsibility which protects subject from outer antigen to keep normal vital condition. This study was aimed to investigate correlative effects of Yookmijihwangtang water abstract on the RBC, WBC, blood CD4+ T helper cell count, blood testosterone, blood cAMP and blood cortisol. 40 Sprague-Dawley male rats were divided into 5 groups(Normal, Control, Sample I, Sample II, Sample III), 6 animals in every group. Normal group was not treated anything, control group was administrated normal saline in the same dosage of Sample I. 3 Sample groups were received some of Yookmijihwangtang water abstract at one time per 24 hours during 5 days in different dosage. Sample I(1/310pack/ml), Sample II(1/62pack/ml), Sample III(1/2.4pack/ml). After finishing treatment, all experimental subjects were killed for blood sample on RBC, WBC, blood CD4+ T helper cell count, spleen CD4+ T helper cell count, axillary lymph node CD4+ T helper cell count. blood cAMP, blood testosterone and blood cortisol. The results were as follows; RBC and WBC were increased in all sample groups. Blood CD4+ T helper cell count(CD4+ T cell count in the blood/whole lymphocyte count in the blood ${\times}100%$) was Normal $46.17{\pm}5.88$, Control $44.50{\pm}4.37$, Sample I $53.00{\pm}2.28$, Sample II $53.83{\pm}3.87$, Sample III $52.17{\pm}2.93$. By the 95% Duncan ANOVA all experimental groups(sample I, Sample II, Sample III) showed slight significant difference from Normal and Control. Blood cAMP(nmol/l) were Normal $1.12{\pm}0.17$, Control $1.16{\pm}0.32$, Sample I $0.46{\pm}0.07$, Sample II $0.44{\pm}0.04$, Sample III $0.54{\pm}0.04$. All experimental groups were singificantly different from both Normal and Control groups(p<0.05). Blood cortisol(nl/ml) were Normal $100.00{\pm}2.00$ Control $90.00{\pm}4.00$, Sample I $440.00{\pm}5.00$, Sample II $520.00{\pm}40.00$, Sample III $470.00{\pm}7.00$. Blood cortisol of all experimental groups were significantly increased(p<0.05). The results suggest that Yookmijihwangtang water abstract could be administrated to patients who have some diseases insufficient essence.

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CMOS 스위치드 캐패시터 방식의 가청주파수대 5차 타원 저역 통과 여파기의 설계 및 구현 (Design of the 5th-order Elliptic Low Pass Filter for Audio Frequency using CMOS Switched Capacitor)

  • 송한정;곽계달
    • 전자공학회논문지C
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    • 제36C권1호
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    • pp.49-58
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    • 1999
  • 본 논문에서는 통과 대역폭이 5KHZ, ripple이 0.1dB이하인 스위치드 캐패시터(Switched Capacitor) 필터를 $0.8{\mu}m$ single poly CMOS ASIC 표준 공정을 이용하여 집적화된 단일 칩으로 제작하였다. 제안된 5차 타원 저역 통과 필털의 구성은 MOS 스위치와 poly 캐패시터, 5개의 2단 CMOS op-amp로 구성하였다. 필터구현은 LC 수동형으로부터 연속전달함수 H(s)를 구하고 쌍선형 z변환을 통하여 이산전달함수 H(z)으로 바꾸어 2차 바이쿼드(biquad)를 종속 연결하는 빌딩블록 방식을 택하였다. 또한 op-amp의 구동범위를 고려하면서 캐패시터 면적을 감소시킨 스케일링 실시한 동일 특성의 필터를 제작하여 그 특성 변화를 비교, 분석하였다. 측정결과 ${\pm}2.5V$ 전원, 50KHz의 표본 주파수에서 2종의 필터 모두 4.96~4.98KHz의 통과 대역폭에 0.7~0.81dB의 리플, 35~38dB정도의 저지대역 이득감쇠 특성을 보였다.

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