• Transactions on Electrical and Electronic Materials
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• 제6권2호
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• pp.57-62
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• 2005

Using intense pulsed ion beam evaporation technique, we have succeeded in the preparation of poly crystalline silicon thin films without impurities on silicon substrate. Good crystallinity and high deposition rate have been achieved without heating the substrate by using lEE. The crystallinity of poly-Si film has been improved with the high density of the ablation plasma. The intense diffraction peaks of poly-Si thin films could be obtained by using the substrate bias system. The crystallinity and the deposition rate of poly-Si thin films were increased by applying (-) bias voltage for the substrate.

• 한국결정성장학회지
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• 제20권6호
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• pp.254-261
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• 2010

본 연구에서는 다결정 실리콘 태양전지 응용을 위한 다결정 실리콘 씨앗층의 제조와 그의 특성에 관한 연구를 수행하였다. 다결정 실리콘 씨앗층은 glass/Al/$Al_2O_3$/a-Si 구조를 이용하여 aluminum-induced layer exchange(ALILE) 고정으로 제조하였으며, 자연산화막부터 50 nm까지 다양한 크기로 $Al_2O_3$ 막두께를 변화시켜 알루미늄 유도 결정화 공정에서 막의 두께가 결정화 특성 및 결정결함, 결정크기에 미치는 영향에 대하여 조사하였다. 연구결과, ALILE 공정으로 생성된 다결정 실리콘막의 결함은 $Al_2O_3$ 막의 두께가 증가할수록 함께 증가한 반면, 결정화 정도와 결정입자의 크기는 $Al_2O_3$막의 두께가 증가할수록 감소하였다. 본 실험에서는 16 nm 두께 이하의 앓은 $Al_2O_3$ 막의 구조에서 평균 약 $10\;{\mu}m$ 크기의 sub-grain 결정립을 얻었으며, 결정성은 <111> 방향의 우선 배향성 특성을 보였다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2001년도 추계학술발표회 초록집
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• pp.68-68
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• 2001

Thin films of polycrystalline silicon (poly-Si) is a promising material for use in large-area electronic devices. Especially, the poly-Si can be used in high resolution and integrated active-matrix liquid-crystal displays (AMLCDs) and active matrix organic light-emitting diodes (AMOLEDs) because of its high mobility compared to hydrogenated _amorphous silicon (a-Si:H). A number of techniques have been proposed during the past several years to achieve poly-Si on large-area glass substrate. However, the conventional method for fabrication of poly-Si could not apply for glass instead of wafer or quartz substrate. Because the conventional method, low pressure chemical vapor deposition (LPCVD) has a high deposition temperature ($600^{\circ}C-1000^{\circ}C$) and solid phase crystallization (SPC) has a high annealing temperature ($600^{\circ}C-700^{\circ}C$). And also these are required time-consuming processes, which are too long to prevent the thermal damage of corning glass such as bending and fracture. The deposition of silicon thin films on low-cost foreign substrates has recently become a major objective in the search for processes having energy consumption and reaching a better cost evaluation. Hence, combining inexpensive deposition techniques with the growth of crystalline silicon seems to be a straightforward way of ensuring reduced production costs of large-area electronic devices. We have deposited crystalline poly-Si thin films on soda -lime glass and SiOz glass substrate as deposited by PVD at low substrate temperature using high power, magnetron sputtering method. The epitaxial orientation, microstructual characteristics and surface properties of the films were analyzed by TEM, XRD, and AFM. For the electrical characterization of these films, its properties were obtained from the Hall effect measurement by the Van der Pauw measurement.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1050-1053
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• 2002

In this paper, Amorphous silicon on glass substrate was recrystallized to poly-crystalline silicon by solid phase crystallization (SPC) technology. The active region of thin film transistor (TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain (LDD) structure was measured and analyzed. As a results, analyzed TFTs reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.185-188
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• 2002

In this paper, Amorphous silicon on glass substrate was recrytallized to poly-crystalline silicon by solid phase crystallization(SPC) technology The active region of thin film transistor(TFT) was fabricated by amorphous silicon. The output and transfer characteristics of thin film transistor with lightly doped drain(LDD) structure was measured and analyzed. As a results, analyzed TFT's reliability with LDD's length by various kinds argument such as sub-threshold swing coefficient, mobility and threshold voltages were evaluated. Stress effects in TFT were able to improve to the characteristics of turn-on current and hot carrier effects by LDD's length variations

• 한국전기전자재료학회논문지
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• 제24권2호
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• pp.112-115
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• 2011

To stabilize the electric characteristic of Silicon Thin Film Transistor, reducing the current leakage is most important issue. To reduce the current leakage, many ideas were suggested. But the increase of mask layer also increased the cost. On this research Bird's Beak process was use to present element. Using Silvaco simulator, it was proven that it was able to reduce current leakage without mask layer. As a result, it was possible to suggest the structure that can reduce the current leakage to 1.39nA without having mask layer increase. Also, I was able to lead the result that electric characteristic (on/off current ratio) was improved compare from conventional structure.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.322-325
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• 2000

N-channel poly-Si TFT, Processed by Solid Phase Crystalline(SPC) on a glass substrate, has been investigated by measuring its electrical properties before and after electrical stressing. It is observed that the threshold voltage shift due to electrical stress varies with various stress conditions. Threshold voltages measured in 1.5$\mu\textrm{m}$ and 3$\mu\textrm{m}$ poly-Si TFTs are 3.3V, 3.V respectively. With the threshold voltage shia the degradation of transconductance(G$\_$m/) and subthreshold swing(S) is also observed.

• 한국전기전자재료학회논문지
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• 제20권2호
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• pp.156-161
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• 2007

This paper describes the characteristics of polycrystalline ${\beta}$ or 3C (cubic)-SiC (silicon carbide) thin films heteroepitaxailly grown on Si wafers with thermal oxide. In this work, the poly 3C-SiC film was deposited by APCVD (atmospheric pressure chemical vapor deposition) method using HMDS (hexamethyildisilane: $Si_{2}(CH_{3}_{6})$ single precursor. The deposition was performed under various conditions to determine the optimized growth conditions. The crystallinity of the 3C-SiC thin film was analyzed by XPS (X-ray photoelectron spectroscopy), XRD (X-ray diffraction) and FT-IR (fourier transform-infrared spectometers), respectively. The surface morphology was also observed by AFM (atomic force microscopy) and voids or dislocations between SiC and $SiO_{2}$ were measured by SEM (scanning electron microscope). Finally, depth profiling was invesigated by GDS (glow discharge spectrometer) for component ratios analysis of Si and C according to the grown 3C-SiC film thickness. From these results, the grown poly 3C-SiC thin film is very good crystalline quality, surface like mirror and low defect. Therfore, the poly 3C-SiC thin film is suitable for extreme environment, Bio and RF MEMS applications in conjunction with Si micromaching.

• 한국결정성장학회지
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• 제3권1호
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• pp.59-65
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• 1993

저항가열식 고진공증착기를 이용하여 압력센서로 사용될 수 있는 boron이 첨가된 다결정 silicon 박막이 제조되었다. 다결정 silicon 박막은 여러온도에서 quartz 기판위에 증착되었으며, boron은 BN 웨이퍼를 사용하여 확산로에서 doping하였다. $500^{\circ}C$의 기판온도에서 증착된 silicon 박막은 비정질이었으며, $600^{\circ}C$에서 결정을 보이기 시작하였고, $700^{\circ}C$에서 다결정이 되었다. $900^{\circ}C$에서 10분동안 boron을 dopion한 후, 박막의 비저항은 $0.1{\Omega}cm~1.5{\Omega}cm$의 범위에 있었으며, boron 밀도(농도)는 $9.4$\times$10^{15}~2.1$\times${10}^{17}cm^{-3}$이었고, 입자의 크기는 $107{\AA}~191{\AA}$이었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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• pp.279.1-279.1
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• 2016

박막 트랜지스터 (thin film transistor, TFT)는 고밀도, 대면적화로 높은 전자의 이동도가 요구되면서, 비정질 실리콘 (a-Si)에서 다결정 실리콘 (poly-Si) TFT 로 연구되었다. 이에 따라 비정질 실리콘에서 결정질 실리콘으로의 상변화에 대한 결정화 연구가 활발히 진행되었다. 또한, 박막 태양전지 분야에서도 유리기판 위에 비정질 층을 증착한 후에 열처리를 통해 상변화하는 고상 결정화 (solid-phase crystallization, SPC) 기술을 적용하여, CSG (thin-film crystalline silicon on glass) 태양전지를 보고하였다. 이러한 비정질 실리콘 층의 결정화 기술을 결정질 실리콘 태양전지 에미터 형성 공정에 적용하고자 한다. 이 때, 플라즈마화학증착 (Plasma-enhanced chemical vapor deposition, PECVD) 장비로 증착된 비정질 실리콘 층의 열처리를 통한 결정화 정도가 중요한 요소이다. 따라서, 비정질 실리콘 층의 결정화에 영향을 주는 인자에 대해 연구하였다. 비정질 실리콘 증착 조건(H2 가스 비율, 도펀트 유무), 실리콘 기판의 결정방향, 열처리 온도에 따른 결정화 정도를 엘립소미터(elipsometer), 투과전자현미경 (transmission electron microscope, TEM), 적외선 분광기 (Fourier Transform Infrared, FT-IR) 측정을 통하여 비교 하였다. 이를 기반으로 결정화 온도에 따른 비정질 실리콘의 결정화를 위한 활성화 에너지를 계산하였다. 비정질 실리콘 증착 조건 보다 기판의 결정방향이 결정화 정도에 크게 영향을 미치는 것으로 확인하였다.