• Journal of Korea Multimedia Society
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• 제4권1호
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• pp.82-90
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• 2001

Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

• The KIPS Transactions:PartA
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• 제17A권1호
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• pp.33-44
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• 2010

We present a pipeline monitoring system based on bio-memetic robot in this paper. A bio-memetic robot exploring pipelines measures temperature, humidity, and vibration. The principal function of pipeline monitoring robot for the exploring pipelines is to recognize the shape of pipelines. We use infrared distance sensor to recognize the shape of pipelines and potentiometer to measure the angle of motor mounting infrared distance sensor. For the shape recognition of pipelines, the number of detected pipelines is used during only one scanning of distance. Three fuzzy classifiers are used for the number of detected pipelines, and the classifying results are presented in this paper.

• International journal of advanced smart convergence
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• 제10권4호
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• pp.278-288
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• 2021

Recently, IoT systems are cloud-based, so that continuous and large amounts of data collected from sensor nodes are processed in the data server through the cloud. However, in the centralized configuration of large-scale cloud computing, computational processing must be performed at a physical location where data collection and processing take place, and the need for edge computers to reduce the network load of the cloud system is gradually expanding. In this paper, a cluster system consisting of 6 inexpensive Raspberry Pi boards was constructed to perform fast data processing. And we propose "Kubernetes cluster system(KCS)" for processing large data collection and analysis by model distribution and data pipeline method. To compare the performance of this study, an ensemble model of deep learning was built, and the accuracy, processing performance, and processing time through the proposed KCS system and model distribution were compared and analyzed. As a result, the ensemble model was excellent in accuracy, but the KCS implemented as a data pipeline proved to be superior in processing speed..

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제41권3호
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• pp.55-64
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• 2004

In this paper, we propose an efficient FFT algorithm for high speed multimedia communication systems, and present its pipeline implementation results. Since the proposed algorithm is based on the radix-4 butterfly unit, the processing rate can be twice as fast as that based on the radix-2$^3$ algorithm. Also, its implementation is more area-efficient than the implementation from conventional radix-4 algorithm due to reduced number of nontrivial multipliers like using the radix-23 algorithm. In order to compare the proposed algorithm with the conventional radix-4 algorithm, the 64-point MDC pipelined FFT processor based on the proposed algorithm was implemented. After the logic synthesis using 0.6${\mu}{\textrm}{m}$ technology, the logic gate count for the processor with the proposed algorithm is only about 70% of that for the processor with the conventional radix-4 algorithm. Since the proposed algorithm can be achieve higher processing rate and better efficiency than the conventional algorithm, it is very suitable for the high speed multimedia communication systems such as WLAN, DAB, DVB, and ADSL/VDSL systems.

• Journal of the Korean Institute of Telematics and Electronics B
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• 제32B권10호
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• pp.1314-1325
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• 1995

In this paper, we describe hardware implementation of VSB (Vestigial SideBand) mo-dulation equalization systems for HDTV (High Definition TeleVision). By modifying an adaptive equalization algorithm, we propose a hardware architecture with a low hardware cost and the performance close to floating-point operations. We also employ the pipeline concept to reduce the hardware cost. The effectiveness of the proposed hardware architecture is de- monstrated through computer simulation and the optimization result of VHDL circuit descriptions.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.415-418
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• 2004

This paper describes a VLSI implementation of BLAST detection for MIMO-OFDM systems. To achieve high speed requirement, we propose the fully pipeline architecture for BLAST structure. This design is implemented using $0.18{\mu}m$ CMOS technology. For a 4-transmit and 4-receive antennas system, it takes $7.5{\mu}s$ to calculate nulling vector and detection order from 48 channel matrixes.

• Journal of IKEEE
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• 제22권1호
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• pp.104-109
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• 2018

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

• Journal of the Institute of Electronics Engineers of Korea SP
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• 제46권1호
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• pp.104-110
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• 2009

In this paper, we suggest a new technique which employ the pipelined architecture for the implementation of the SAP adaptive filter using variable step size. According as SAP adaptive filter is sufficiently decomposed, a simplified SAP adaptive filter can be derived, and the weights of adaptive sub-filters can be updated by a simple formular without a matrix inversion. The convergence speed and the steady state error of the simplified SAP adaptive filter are improved by using variable step size. For practical implementation, the simplified SAP adaptive sub-filters are transformed by the pipeline technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제24권9A호
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• pp.1419-1424
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• 1999

In order to implement morphological filters on image processing systems, the size of structuring element must be small due to the architectural constraints of the systems, which requires the decomposition of structuring element into small elements for the filters with large structuring elements. In this paper, an algorithm for decomposition of structuring element with no restriction on the shape and size is developed which enables sub-optimal implementation of any morphological filter on 3X3 pipeline machine. The given structuring element is first decomposed into the union of elements using sequential search procedure, then each element is further decomposed optimally into 3X3 elements, resulting in final sub-optimal 3$\times$3 hybrid decomposition. The proposed algorithm is applied to some structuring elements and the results close to the optimum are obtained.

• Smart Media Journal
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• 제4권4호
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• pp.39-46
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• 2015

This paper describes hardware implementation of the encryption block of the '128 bit block cipher LEA' among various lightweight encryption algorithms for IoT (Internet of Things) security. Round function blocks and key-schedule blocks are designed by parallel circuits for high throughput. The encryption blocks support secret-key of 128 bits, and are designed by FSM method and 24/n stage(n=1, 2, 3, 4, 8, 12) pipeline methods. The LEA-128 encryption blocks are modeled using Verilog-HDL and implemented on FPGA, and according to the synthesis results, minimum area and maximum throughput are provided.