Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Hardware Design and Implementation of Block Encryption Algorithm ARIA for High Throughput

High Throughput을 위한 블록 암호 알고리즘 ARIA의 하드웨어 설계 및 구현

  • Yoo, Heung-Ryol (Dept. of Mechanical Facility Control Engineering, Korea University of Technology and Education) ;
  • Lee, Sun-Jong (Dept. of Mechanical Facility Control Engineering, Korea University of Technology and Education) ;
  • Son, Yung-Deug (Dept. of Mechanical Facility Control Engineering, Korea University of Technology and Education)
  • Received : 2018.03.09
  • Accepted : 2018.03.28
  • Published : 2018.03.31
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Abstract

This paper presents a hardware design for the block encryption algorithm of ARIA which is used for standard in Korea. It presents a hardware-efficient design to increase the throughput for the ARIA algorithm using a high-speed pipeline architecture. We have used ROM for the S-box implementation. This approach aims to decrease the critical path delay of the encryption. In this paper, hardware was designed by VHDL, realized RTL level by Synplify which is synthesis tool and verified simulation by ModelSim. The ARIA algorithm is shown 68.3 MHz (Maximum operation frequency) to use Xilinx VertxE XCV Series device.

본 논문에서는 국내 표준으로 제정된 ARIA 알고리즘을 High Throughput을 위한 하드웨어 구조를 제안하고 구현하였다. 치환 계층의 고속 처리를 위하여 ROM table 구성과 라운드 내부의 파이프라인 방식을 이용하며, 12 라운드를 확장된 구조로 설계하여 병렬 특성을 활용 가능한 설계 방법을 제안한다. 본 논문은 VHDL을 이용하여 RTL 레벨로 설계 되었으며, 합성 툴인 Synplify를 이용하였으며, 시뮬레이션을 위해 ModelSim을 이용하였다. 본 논문에서 제시한 하드웨어 구조는 Xilinx VertxeE Series 디바이스를 이용하였으며 68.3 MHz의 주파수 및 674Mbps의 Throughput을 나타낸다.

Keywords

References

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