• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.621-622
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• 2006

This paper presents the design of LVDS(Low-Voltage-Differential-Signaling) driver circuit for Gb/s-per-pin operation using BiCMOS process technology. To reduce chip area, LVDS driver's switching devices were replaced with lateral bipolar devices. The designed lateral bipolar transister's common emitter current gain($\beta$) is 20 and device's emitter size is 2*10um. Also the proposed LVDS driver is operated at 2.5V and the maximum data rate is 2.8Gb/s approximately.

• Nuclear Engineering and Technology
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• v.31 no.3
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• pp.303-313
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• 1999

Various interpolation methods have been compared for reconstruction of LMR pin power distributions in hexagonal geometry. Interpolation functions are derived for several combinations of nodal quantities and various sets of basis functions, and tested against fine mesh calculations. The test results indicate that the interpolation functions based on the sixth degree polynomial are quite accurate, yielding maximum interpolation errors in power densities less than 0.5%, and maximum reconstruction errors less than 2% for driver assemblies and less than 4% for blanket assemblies. The main contribution to the total reconstruction error is made tv the nodal solution errors and the comer point flux errors. For the polynomial interpolations, the basis monomial set needs to be selected such that the highest powers of x and y are as close as possible. It is also found that polynomials higher than the seventh degree are not adequate because of the oscillatory behavior.

• ETRI Journal
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• v.30 no.4
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• pp.612-614
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• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• Journal of Institute of Control, Robotics and Systems
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• v.14 no.6
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• pp.543-547
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• 2008

In the paper, we develop the ultrasonic bonding technique for LCD driver chips having small size and high pin-density. In general, the mounting technology for LCD driver ICs is a thermo-compression method utilizing the ACF (An-isotropic Conductive Film). The major drawback of the conventional approach is the long process time. It will be shown that the conventional ACF method based on thermo-compression can be remarkably enhanced by employing the ultrasonic bonding technique in terms of bonding time. The proposed approach is to apply the ultrasonic energy together with the thermo-compression methodology for the ACF bonding process. To this end, we design a bonding head that enables pre-heating, pressure and ultrasonic excitation. Through the bonding experiments mainly with LCD driver ICs, we present the procedures to select the best combination of process parameters with analysis. We investigate the effects of bonding pressure, bonding time, pre-heating temperature before bonding, and the power level of ultrasonic energy. The addition of ultrasonic excitation to the thermo-compression method reduces the pre-heating temperature and the bonding process time while keeping the quality bonding between the LCD pad and the driver IC. The proposed concept will be verified and demonstrated with experimental results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.6
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• pp.97-104
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• 2010

In this paper, ICT (in circuit tester) inspection system and inspection algorithm is proposed and detects whether inferiority exists or not in the mounted device on the flexible PCB in cell phones or mobile display devices. The system is composed of PD (pin-driver) and GGM (ground guarding method). The structural characteristics of these flexible PCB are analyzed, which is needed to input or output the test signal. Test signal to investigate the characteristics of passive components is generated using modified circuit diagram and proposed inspection algorithm. PM (pin-map) is decided on the basis of circuit diagram and has the information about the kind of test signal to be applied and the pad number for the test signal to be connected. PD is designed to load a proper test signal for a specific pad and is adjusted according to PM so that the reconstructed circuit has minimum node and mash. The proposed ICT inspection system is realized using PD and GGM. Using the system, an experiment for each passive component is done to investigate the measurement accuracy of the developed system and an experiment for real flexible PCB model is done to verity the effectiveness of the system.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• ETRI Journal
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• v.27 no.1
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• pp.81-88
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• 2005

In this paper, interface circuits that are suitable for point-to-point interconnection with an over 1 Gbps data rate per pin are proposed. To achieve a successful data transfer rate of multi-gigabits per-second between two chips with a point-to-point interconnection, the input receiver uses an on-chip parallel terminator of the pass gate style, while the output driver uses the pullup and pulldown transistors of the diode-connected style. In addition, the novel dynamic voltage level converter (DVLC) has solved such problems as the access time increase and valid data window reduction. These schemes were adopted on a 64 Mb DDR SRAM with a 1.5 Gbps data rate per pin and fabricated using a 0.10 ${\mu}m$ dual gate oxide CMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.5
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• pp.451-458
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• 2002

Absorptive type SP3T(Single Pole Three Throw) and SP8T switch modules over the 6-18 GHz are designed and fabricated. The epitaxial structure of GaAs PIN diode for switch modules are designed for low loss and high power capability. The maximum input power of SP3T and SP8T switch modules are 2 W and 1 W, respectively. The switching time with driver circuit is less than 130 nsec. The maximum insertion loss of SP3T switch module and SP8T module shows 2.8 dB and 4.2 dB, respectively. The isolation between input port and output port is more than 55 dB. Two switch modules for electronic warfare system have passed the environment tests of the related test items.

• Journal of the Korea Safety Management & Science
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• v.20 no.3
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• pp.21-26
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• 2018

This paper describes result of a study on safety against a fire of charging cable for mobile phone for vehicle. Combustion on the USB cable in the car was happened while driving. Gas coming from the burning USB cable could be a reason which can make a secondary car accident since the driver also can be embarrassed while driving. In order to prevent a secondary car accident connected on the road, to research a reason why USB cable can emit gas and be burned in charging. We did simulation test with abnormal fault condition for the electronic component on the board in the USB cable. So we get the result from abnormal fault condition simulation test, for instance, shorted test for output terminal of 8 pin switch, shorted test for chip resistor after thermal aging in the condition $25^{\circ}C$, 93 % RH during 48 hours. To analysis the result of all test, Combustion on the USB cable was not the 8 pin but other electrical component such as a chip resistor. Therefore we guess that the reason for USB cable combustion in charging in a car was not 8 pin and a LED but another defective component.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.653-654
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• 2006

A Pre-emphasis transmitter for DRAM bus system has achieved 3.2Gbps/pin operation at 1.8V supply voltage with 0.18um CMOS process. The transmitter has 800MHz PLL to generate 4 phase clocks. The 4 phase clocks are used for input clock of PRBS and multiplexing. One tap pre-emphasis is used to reduce inter symbol interference (ISI) caused by channel low pass effects. The analog calibration makes the optimized driver impedance independent with the PVT variation.