• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.735-738
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• 2005

디지털 신호의 위상 에러는 랜덤 특성을 갖는 위상 잡음과 도플러에 의한 추적 위상 에러에 의해 발생된다. 도플러 현상이 나타나는 움직임을 갖는 이동형 위성통신 시스템에서 위상 잡음과 더불어 static 위상 오차에 의한 전송 신호의 영향을 해석하여 이동형 위성통신 시스템에 적합한 시스템 요구 위상 잡음 스펙트럼을 설계하여야 한다. 본 논문에서는 이동형 양방향 위성통신 시스템의 비대칭 이동 서비스에 대한 도플러 영향과 위상 에러를 해석하여 요구되는 전송 시스템의 위상 잡음 스펙트럼을 설계하고, 움직임을 갖는 단말국의 도플러 영향을 최소화하는 전송 서비스를 해석한다. 제안된 위상 잡음 스펙트럼은 요구되는 전송 시스템에 대한 주파수 발생부를 설계할 수 있도록 한다.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.158-162
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• 2015

A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.

• 한국위성정보통신학회논문지
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• 제6권1호
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• pp.45-49
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• 2011

본 논문에서 위성통신 단말에 적용할 PLL 주파수 합성기의 잡음 특성을 분석하였고, 주파수 간격(step size)을 작게하면서 저 위상잡음 특성을 갖도록 설계 및 구현하였다. 구현된 주파수 합성기 모듈은 950~1450 MHz 대역에서 -2dBm 이상의 출력을 보였으며, 위상잡음은 10kHz offset에서 -101dBc/Hz로 측정되었다. 주파수 합성기의 위상잡음 특성을 분석한 결과 루프대역 내에서의 위상잡음은 분주기 값을 작게 하기위한 LO의 특성을 따라 감을 알 수 있었다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.649-659
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• 2003

OFDM/FH communication system Is widely used in the wireless communication for the large capacity and high-speed data transmission. However, phase noise and PAPR (peak-to-average power ratio) are the serious problems causing performance impairment. In this paper, PLL (phase locked loop) frequency synthesizer with high switching speed is used for the phase noise model. SSPA and TWTA are considered for the nonlinear HPA model. Under these conditions and by approximating $e^{j{\phi}[m]}$ into $1 + j{\phi}[m]-\frac{1}{2}{\phi}^2[m]$ for the phase noise nonlinear approximation, SINR (signal-to-interference-noise-ratio) with nonlinear HPA and phase noise is derived in the OFDM/FH system. The bit error probabilities (BER) are found by computer simulation method and semi-analytical method. The simulation results closely match with the semi-analytical results.

• ETRI Journal
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• 제18권3호
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• pp.147-160
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• 1996

We investigate noise-induced phase transitions in globally coupled active rotators with multiplicative and additive noises. In the system there are four phases, stationary one-cluster, stationary two-cluster, moving one-cluster, and moving two-cluster phases. It is shown that multiplicative noise induces a bifurcation from one-cluster phase to two-cluster phase. Pinning force also induces a bifurcation from moving phase to stationary phase suppressing the multiplicative noise effect. Additive noise reduces both effects of multiplicative noise and pinning force urging the system to the stationary one-cluster phase. The frustrated effects of pinning force and additive and multiplicative noises lead to a reentrant transition at intermediate additive noise intensity. Nature of the transition is also discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.501-503
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• 2008

This paper presents the design of a 2.4 GHz low phase noise fully integrated LC Voltage-Controlled-Oscillator (VCO) in $0.18{\mu}m$ CMOS technology. The VCO is without any tail bias current sources for a low phase noise and, in which differential varactors are adopted for the symmetry of the circuit. At the same time, the use of differential varactors pairs reduces the tuning range, i.e., the frequency range versus VTUNE, so that the phase noise becomes lower. The simulation results show the achieved phase noise of -138.5 dBc/Hz at 3 MHz offset, while the VCO core draws 3.9mA of current from a 1.8V supply. The tuning range is from 2.28GHz to 2.55 GHz.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.903-905
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• 2005

링발진기의 위상잡음을 줄이기 위한 이론적인 기초를 소개한다. 위상잡음과 링발진기의 설계 파라메타의 관계를 이해함으로써 위상잡음을 설계 단계에서 줄이는 효과를 볼 수 있다. 기존의 참고 문헌을 통해 얻어진 위상잡음과 설계 파라메타의 관계를 통해 위상잡음을 줄이는 방법을 제시한다.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 춘계학술대회
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• pp.679-681
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• 2014

본 논문에서는 M-ary APSK 변조 방식을 사용하는 통신 시스템의 위상잡음에 의한 영향을 분석한다. 고차 변조 방식의 신호 성상도를 고려하여 위상 잡음에 의한 성능을 모의 분석한다. PSK 저차 변조 방식에 의한 성능 분석도 수행하며, 분석 결과는 해석적 모델의 성능 열화 결과와 비교 평가한다. 비교 평가된 분석 모델을 통하여 고차 변조 방식을 사용하는 통신 시스템의 위상잡음에 의한 열화 정도를 제시한다.

• 한국소음진동공학회논문집
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• 제21권10호
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• pp.916-923
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• 2011

The refrigerant after the expansion valve interchanges the heat at the evaporator. At this moment, the state of gas and liquid becomes two-phase flow and causes irregular noise. In order to avoid the noise, the two-phase flow pattern should be predicted. In this paper, the procedure to predict the two-phase flow patterns such as churn flow and annular flow was suggested using the CFD software. The experiments using refrigerant-supplying equipment was carried out and the noise levels according to the flow pattern were measured. The flow patterns predicted by this procedure showed good agreement with those by experiments. The churn flow is noisier than annular flow pattern.

• Journal of Multimedia Information System
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• 제5권2호
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.