• Proceedings of the KIEE Conference
• /
• 2004.11c
• /
• pp.705-707
• /
• 2004

In this paper, we propose a robust control technique against parameter uncertainties as well as external disturbances. It is robust control scheme using discrete-time state space disturbance observer. It does not require disturbance modeling, plant inverse modeling and/or Q filter. In frequency domain, its performance is evaluated in terms of sensitivity and complementary sensitivity as well as gain and phase margin. Finally we discuss design criterion of state space disturbance observer considering its performance in frequency domain.

• Proceedings of the KSR Conference
• /
• 2004.06a
• /
• pp.1381-1385
• /
• 2004

This paper presents a modelling methodology using fuzzy logic and train performance simulation for determining an economical running pattern for a high speed train which minimizes energy consumption under an given trip margin. The economical running pattern is defined with an economical maximum speed in traction phase, a speed at the end of coasting. As a case study, the simulation is carried out for an economical run of korea high speed train prototype, and the results of fuzzy model described.

• 제어로봇시스템학회:학술대회논문집
• /
• 1993.10a
• /
• pp.139-144
• /
• 1993

In this paper, a robust reduced order adaptive controller is proposed based on Internal Model Control(IMC) structure for stochastic linear stable systems. The concept of gain margin is utilized to make the adaptive IMC controller robust. We prove the stability of the proposed adaptive IMC system for stable plants under the assumption that upper bounds for system orders are known. Simulation results show that the proposed method has good performance and stability robustness.

• 제어로봇시스템학회:학술대회논문집
• /
• 1993.10a
• /
• pp.491-497
• /
• 1993

In MIMO design, input and output units are different from each other. By this reason, the effect of larger units to smaller one is not trivial and there is no method of proper scaling, optimal scaling. In this paper, robust stability of MIMO LQG/LTR design are analised when the plnat inputs and outputs are scalled. The upper bound of model error to guarantee the robust stability is obtained, and gain margin and phase margins are computed with respect to scalling matrices.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.2
• /
• pp.396-406
• /
• 2007

In this paper, we proposed development of improved model reduction and design of hierarchical controller using reduction model. The model reduction is considered that it is the transient response and the steady-state response through the use of nyquist curve. The hierarchical controller selected tuning of PID controller to ensure specified gain and phase margin and hybrid smith-predictor fuzzy controller using reduction model. Simulation examples are given to show the better performance of the proposed method than conventional methods.

• Proceedings of the KAIS Fall Conference
• /
• 2003.06a
• /
• pp.239-242
• /
• 2003

Scale down으로 인해 부족해진 overlay margin을 통해 충분히 확보해주고, 이와 동시에 attPSM(attenuated phase shift)의 사용으로 발생하는 side-lobe 현상을 억제하기 위한 방법으로 rule-based OPC(optical proximity correction)룰 사용하여 side-lobe만을 효과적으로 추출한 후, 그 자리에 scattering bar를 삽입하였다. 그리고 ORC(optical rule checking)를 통해 original layout과 aerial image의 EPEs(edge placement errors)를 검사하여 검증에 걸리는 시간을 감소시켰다.

• Proceedings of the KIEE Conference
• /
• 1991.07a
• /
• pp.720-725
• /
• 1991

In this thesis, the lead-lag compensator is designed to improve output characteristics of flyback zero voltage switching quasi-resonant converters. The switch and the diode are assumed ideally. And the SMPS is modelled by state equations with four operation modes. And the model for controller design is also achived by using a state space averaging method, which is continuous time average of state variables every period. The lag, the lead and the lead-lag compensator is designed the SMPS respectively. The time domain analysis and the frequency domain analysis are done for each compensated circuit. It is possible increasing the phase margin and improving the transient response by the compensators. The phase lag compensator has small overshoot comparatively. But the bandwidth is narrower than the others, so it has longest settling time. For the phase lead compensator, the response come to steady-state within short period. But the overshoot is the largest due to its large peak gain. Finally, the phase lead-lag compensator has medium characteristics in the overshoot and the settling time.

• Journal of Korea Society of Industrial Information Systems
• /
• v.21 no.4
• /
• pp.21-30
• /
• 2016

In a single-phase power factor correction (PFC), the standard cascaded control algorithm using a proportional-integral-derivative (PID) controller has two main drawbacks: an inability to track sinusoidal current reference and low harmonic compensation capability. These drawbacks cause poor power factor and high harmonics in grid current. To improve these drawbacks, this paper uses a proportional-integral-derivative-resonant (PIDR) controller which combines a type-III PID with proportional-resonant (PR) controllers in the PFC. Based on a small signal model of the PFC, the type-III PID controller was implemented taking into account the bandwidth and phase margin of the PFC system. To adopt the PR controllers, the spectrum of inductor current of the PFC was analyzed in frequency domain. The hybrid PIDR controller were simulated using PSCAD/EMTDC and implemented on a 3 kW PFC prototype hardware. The performance results of the hybrid PIDR controller were compared with those of an individual type-III PID controller. Both controllers were implemented successfully in the single-phase PFC. The total harmonic distortion of the proposed controller were much better than those of the individual type-III PID controller.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2005.07a
• /
• pp.15-16
• /
• 2005

Chalcogenide phase change memory has high performance to be next generation memory, because it is a nonvolatile memory processing high programming speed, low programming voltage, high sensing margin, low consumption and long cycle duration. We have developed a new material of PRAM with $Ge_1Se_1Te_2$. This material has been propose to solve the high energy consumption and high programming current. We have investigated the phase transition behaviors in function of various process factor including contact size, cell size, and annealing time. As a result, we have observed that programming voltage and writing current of $Ge_1Se_1Te_2$ are more improved than $Ge_2Sb_2Te_5$ material.

• Journal of Power Electronics
• /
• v.18 no.6
• /
• pp.1780-1790
• /
• 2018

Voltage feed-forward control (VFFC) is widely used in LCL-type grid-tied inverters due to its advantages in terms of disturbance rejection performance and fast dynamic response. However, VFFC may worsen the stability of inverters under weak grid conditions. It is revealed in this paper that a large phase-lag in the low-frequency range is introduced by VFFC, which reduces the phase margin significantly and leads to instability. To address this problem, a novel virtual-impedance-based control, where a phase-lead is introduced into the low-frequency area to compensate for the phase lag caused by VFFC, is proposed to improve system stability. The proposed control is realized with a high-pass filter, without high-order-derivative components. It features easy implementation and good noise immunity. A detailed design procedure for the virtual impedance control is presented. Both theoretical analysis and experimental results verify the effectiveness of the control proposed.