• 한국정보통신학회논문지
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• 제25권5호
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• pp.677-684
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• 2021

본 논문은 절대 시간 측정 가능한 시간 디지털 변환기에 대한 논문으로 제안하는 시간 디지털 변환기는 0.18-um CMOS 공정을 이용하여 설계 되었고 IC로 제작하여 검증하였다. 설계된 시간 디지털 변환기는 라이다 시스템에 적용하기 위하여 긴 측정시간과 절대적인 50ps를 측정할 수 있어야하는데 위상고정루프의 625MHz 클록을 기준클록으로 사용하기 때문에 절대시간의 측정이 가능하며 디지털 보정회로를 이용하여 어떤 상황에서 든 50ps의 분해능을 가질 수 있다. 기준클록을 카운터하여 큰 시간 단위의 측정을 할 수 있어 최대 800ns의 시간이 측정가능하고 딜레이 체인을 이용하여 정밀한 시간 값을 측정 할 수 있다. 결과적으로 제작된 시간 디지털 변환기는 50ps 단위로 시간을 측정할 수 있는데 최대 오차는 INL 0.8-LSB정도이며 1.8V 인가전압에 전력 소모는 약 70mW 정도이다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2002년도 종합학술발표회 논문집 Vol.12 No.1
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.36-42
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• 2008

본 논문은 광통신-시리얼 링크를 위한 40Gb/s 클록 및 데이터 복원 회로의 설계를 제안한다. 설계된 본 회로는 다중 위상을 생성하는 LC 탱크 PLL을 이용하여 8개의 샘플링 클록을 생성하고 $2{\times}$ 오버샘플링 구조의 뱅-뱅 위상 검출기를 이용하여 데이터와 클록의 위상을 조정한다. 40Gb/s의 입력 데이터가 샘플링을 거쳐서 1:4 디멀티플렉싱되어 4채널에 10Gb/s 출력으로 복원되는 구조로서 디지털과 아날로그의 전원을 분리하여 설계가 진행되었다. 인덕터를 사용하여 칩면적은 $2.8{\times}2.4mm^2$을 차지하고 전력소모는 약 200mW이다. 0.18um CMOS공정으로 칩 제작후 측정결과 채널당 악 9.5Gb/s 출력이 측정되었다(직렬입력 약 38Gb/s 해당).

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.

• Journal of Power Electronics
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• 제11권5호
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• pp.632-638
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• 2011

This paper presents a cascaded coil flux control based on a Current Source Parallel Resonant Push-Pull Inverter (CSPRPI) for Induction Heating (IH) applications. The most important problems associated with current source parallel resonant inverters are start-up problems and the variable response of IH systems under load variations. This paper proposes a simple cascaded control method to increase an IH system's robustness to load variations. The proposed IH has been analyzed in both the steady state and the transient state. Based on this method, the resonant frequency is tracked using Phase Locked Loop (PLL) circuits using a Multiplier Phase Detector (MPD) to achieve ZVS under the transient condition. A laboratory prototype was built with an operating frequency of 57-59 kHz and a rated power of 300 W. Simulation and experimental results verify the validity of the proposed power control method and the PLL dynamics.

• 대한전자공학회논문지SD
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• 제46권9호
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• pp.74-80
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• 2009

본 논문은 싱글의 LC-탱크 전압제어발진기(VCO)를 사용한 $2{\sim}6GHz$의 CMOS 주파수 합성기에 관하여 기술하였다. 광대역에서 동작하는 주파수 합성기 설계를 위해 최적화된 로컬발진기(LO) 신호 발생기를 사용하였다. LO 신호 발생기는 LC-탱크 VCO와 이 신호를 분주하고 혼합하는 방법으로 광대역의 주파수에서 동작하도륵 구현하였다. 주파수 합성기는 3차 1-1-1 MASH 타입의 시그마-델타 모듈레이터(SDM)를 사용한 소수 분주 위상잠금루프(PLL)에 기초로 설계되었다. 제안한 주파수 합성기는 $0.18{\mu}m$ CMOS 공정기술을 사용하여 설계하였고, off-chip 루프 필터를 가지고 $0.92mm^2$의 칩 면적을 차지하며, 1.8V 전원에서 36mW 이하의 전력을 소모한다. PLL은 $8{\mu}s$보다 적은 시간에서 록킹을 완료한다. 위상 잡음은 중심 주파수 신호로부터 1MHz 오프셋에서 -110dBc/Hz보다 작다.

• Journal of Power Electronics
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• 제16권2호
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• pp.704-716
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• 2016

Small distributed generation units are usually connected to the main electric grid through single-phase voltage source inverters. Grid operating conditions such as voltage and frequency are not constant and can fluctuate within the range values established by international standards. Furthermore, the requirements in terms of power factor correction, total harmonic distortion, and reliability are getting tighter day by day. As a result, the implementation of reliable and efficient control algorithms, which are able to adjust their control parameters in response to changeable grid operating conditions, is essential. This paper investigates the configuration topology and control algorithm of a single-phase inverter with the purpose of achieving high performance in terms of efficiency as well as total harmonic distortion of the output current. Accordingly, a Second Order Generalized Integrator with a suitable Phase Locked Loop (SOGI-PLL) is the basis of the proposed current and voltage regulation. Some practical issues related to the control algorithm are addressed, and a solution for the control architecture is proposed, based on resonant controllers that are continuously tuned on the basis of the actual grid frequency. Further, intentional islanding operation is investigated and a possible procedure for switching from grid-tied to islanding operation and vice-versa is proposed.

• 대한전자공학회논문지
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• 제24권4호
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• pp.548-552
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• 1987

The constraint condition of the loop filter is persented for the convergence of the random jitter accumulation fo the 2-nd order PLL (phase-locked loop) circuit used in digital regenerative repeater. This condition is confirmed under the assumption that the number of repeater chain is 5, bandwidth is 100. 0KHz, the power spectral density of white Gaussian noise is 1.0x10**-6 [W/Hz]. Also, it is shown that if the condition is satisfied, the accumulated random jitter and the alignment jitter will have the saturation characteristics.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.232-233
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• 2012

This paper presents an effective control scheme for an electric vehicle battery charger where a symmetrical bridgeless power factor-corrected converter and a buck converter are cascaded. Both converters have been popular in industries because of their high efficiency, low cost, and compact size, hence combining these converters makes the overall battery charging system strongly efficient. Moreover, this charger topology can operate at universal input voltage and attain a desired battery current and voltage without ripple. In order to achieve a unity input power factor and zero input current harmonic distortion, the proposed control scheme adopts duty ratio feed-forward control technique in both current and voltage control loop. Additionally, in the current loop, its reference is created by a phase-locked loop (PLL) block, leading to a pure sinusoidal input current although the input voltage waveform is being distorted. The feasibility and practical value of the proposed approach are verified by simulation and experiment with an 110V/60Hz ac line input and 1.5kW-72V dc output of the battery charging system.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.649-659
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• 2003

OFDM/FH communication system Is widely used in the wireless communication for the large capacity and high-speed data transmission. However, phase noise and PAPR (peak-to-average power ratio) are the serious problems causing performance impairment. In this paper, PLL (phase locked loop) frequency synthesizer with high switching speed is used for the phase noise model. SSPA and TWTA are considered for the nonlinear HPA model. Under these conditions and by approximating $e^{j{\phi}[m]}$ into $1 + j{\phi}[m]-\frac{1}{2}{\phi}^2[m]$ for the phase noise nonlinear approximation, SINR (signal-to-interference-noise-ratio) with nonlinear HPA and phase noise is derived in the OFDM/FH system. The bit error probabilities (BER) are found by computer simulation method and semi-analytical method. The simulation results closely match with the semi-analytical results.