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40Gb/s Clock and Data Recovery Circuit with Multi-phase LC PLL in CMOS $0.18{\mu}m$  

Ha, Gi-Hyeok (Research Staff, I&C technology)
Lee, Jung-Yong (Research Staff, LG Electronics)
Kang, Jin-Ku (School of Electronic Engineering & Institute for Information and Electronics Research, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.4, 2008 , pp. 36-42 More about this Journal
Abstract
40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).
Keywords
Clock and data recovery (CDR); Phase detector; Bang-Bang PD system; Phase Locked Loop(PLL);
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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