• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.874-877
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• 1987

In this paper a DPLL circuit realizable by digital IC's is propose and the principles of general DPLL are described. An all Digital phase locked loop is designed, analyzed, and tested. In particular, the approach of invoking Gaussian assumption on the decision variable and based on S.O.Rices theory is used. As a performance of the above PLL detector operating on low data rate FSK is given and demonsrtated to be FSK reception.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.691-693
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• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.82-84
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• 2020

본 논문에서는 용기 소음 저감을 위해 Anyplace induction heating (lH) 시스템에 적합한 설계 방안을 제시한다. 다수의 워킹 코일 및 인버터를 적용한 Anyplace lH 시스템에서 인접한 코일들이 서로 다른 동작 주파수로 용기를 가열 할 경우 주파수 차이에 따른 용기 소음이 발생한다. 따라서 용기의 근접 가열 시 발생하는 소음을 저감하기 위한 방안들을 비교 및 분석하고 실험 및 시뮬레이션을 통해 phase locked loop (PLL)을 이용한 교번 pulse density modulation (PDM) 제어를 적용한 시스템 설계 방안에 대한 타당성을 검증한다.

• Proceedings of the KIPE Conference
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• 2011.11a
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• pp.305-306
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• 2011

본 논문에서는 3상 양방향 AC-DC 컨버터의 계통사고 검출기법을 제안한다. 3상 양방향 AC-DC 컨버터는 동기좌표법을 이용하여 PLL(Phase locked loop)을 구현하였고, PLL제어에 있어서 dq변환을 수행한다. dq변환은 입력의 크기 정보와 위상정보를 포함하기 때문에 이를 이용하여 계통사고의 검출이 가능하다. 따라서 본 논문에서는 3상 양방향 AC-DC 컨버터를 이용하여, 계통사고에 대한 검출 기법을 제안하였으며, 계통의 d축, q축 전압대하여 사고를 정의하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.301-306
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• 2005

In this paper, a gain-boosting charge pump(CP) and a latch type voltage controlled oscillato.(VCO) with voltage controlled resistor(VCR) were proposed. The gain-boosting CP achieves good .current matching of less than 11$mu$V voltage difference between 43$mu$V and 32$mu$V in its output range from 0.8V to 2.3V. The VCO with VCR shows good linear characteristics over the range from 1V to 3V. The fabricated VCO exhibits -108dBc/Hz phase noise at a 100kHz and is comparable to that of the integrated LC-tank oscillator. The phase locked loop(PLL) with new circuits was simulated in a 0.35$mu$m CMOS process and showed 150$mu$s locking time.

• Proceedings of the KIEE Conference
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• 2001.11a
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• pp.53-55
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• 2001

A dual probe laser Doppler vibrometer (LDV) that has one laser source and provides two independent object beams has been developed for the first time. An electronic circuit that converts light signal to electronic signal has been also developed using phase locked loop(PLL). It was found that this types of dual probe LDV can be used in differential mode and self-vibration compensation mode.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.209-212
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• 2000

Charge pump based upon a phase locked loop(PLL) is described. This charge pump show that it is possible to overcome the issue of charge pump current mismatch by using a current subtraction circuit. Also, this charge pump can suppress reference spurs and disturbance of the VCO control voltage. HSPICE simulations are performed using 0.25$\mu\textrm{m}$ CMOS process.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.171-172
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• 2017

본 논문에서는 분산전원의 계통 연계형 시스템에서의 단독운전 검출 방식인 RPV(Reactive Power Variation)기법에 대한 고찰과 주파수 검출 방식을 분석한다. IEEE 929 - 2000에 근거하여 RPV 기법에서의 NDZ에 대하여 살펴보고, PLL(Phase Locked Loop) 기법을 이용한 주파수 검출에 대한 분석 및 설계와 이를 통한 단독운전 검출을 하고자 한다. 시뮬레이션을 통하여 타당성을 검증하였다.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.7
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• pp.1241-1249
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• 2007

Lately, many approaches of speed sensorless control method for Interior Permanent Magnet Synchronous Motor(IPMSM) ha, been developed. This paper proposes a novel sensorless algorithm for speed estimation of IPMSM. First of all, proposes sensorless method estimates flux of rotor using foundational voltage equation of IPMSM and then estimates position and speed of rotor using Phase Locked Loop(PLL). Proposed sensorless algorithm demonstrated through simulation using Matlab simulink and experiment.