• 전력전자학회논문지
• /
• 제20권1호
• /
• pp.38-44
• /
• 2015

This paper presents the sensorless drive method for mono inverter dual parallel (MIDP) surface mounted permanent magnet synchronous motor (SPMSM) drive system. MIDP motor drive system is a technique that can reduce the cost of the multi motor driving system. To maximize this merit of the MIDP motor drive system, the sensorless technique is essential to eliminate the position sensors. This paper adopts an appropriate sensorless method for MIDP SPMSM drive system, which uses the reduced order observer and phase locked loop (PLL) to reduce the calculation burden. The I-F control method is implemented for start-up and low speed operation. The validity and performance of the proposed algorithm are shown via experiments with 600-W SPMSMs.

• 대한전자공학회논문지
• /
• 제9권1호
• /
• pp.25-30
• /
• 1972

일정한 패턴의 디지탈·코오드가 검출될 때 마다 "1"이 송출된것으로 하는 디지탈 데이타 통신을 종래 2,400bit/sec.에 한정되었던 유선전화 케이블에 적용하여 속도를 향상시켰다. 코오드늘 "1"의 연속클라스타를 사용하여 수신단에 홰이스·록크드·루우프를 두어 그 여파부분의 시정수를 키워 PLL 고유의 잡음불감특성을 활용함으로서 에라율이 적으면서도 20kbit/sec.의 속도를 얻을 수 있었다.

• 전기전자학회논문지
• /
• 제17권3호
• /
• pp.248-253
• /
• 2013

주파수 판별기는 주파수를 디지털 비트 신호로 변환해주는 회로로서 변조기, 동기화 회로 등에 쓰인다. 본 논문에서는 여러 종류의 일차, 이차 주파수 판별기의 구조를 모델링하고 양자화 잡음 성능을 분석하며, 새로운 구조의 델타-시그마 주파수 판별기 구조를 제안한다. 이론적 분석과 유도된 수식으로부터 출구 잡음을 구하고 모의실험으로 타당성을 검증하였다. 제안된 주파수 판별기는 전 디지털 회로로서 전 디지털 위상 잠금 루프의 궤환 경로에 적용될 수 있다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.193-196
• /
• 2001

One of the major reasons for not integrating a VCO on one-chip in a PLL (phase locked loop) system is the large chip-to-chip variation of the VCO (voltage controlled oscillator) center frequency. In this thesis, a simple bias technique is proposed to compensate the process fluctuation. The proposed bias technique is applied to the VCO and it reduces the deviation of the VCO center frequency from 35% to 8 %. With the suggested bias technique, a 400 MHz frequency synthesizer is designed for general purpose. It utilizes a programmable divider for various division ratio. The design methodology provides the possibility of the one-chip solution for a PLL system.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 추계종합학술대회 논문집
• /
• pp.340-343
• /
• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.

• 전자공학회논문지B
• /
• 제32B권12호
• /
• pp.1644-1651
• /
• 1995

A data and clock recovery integrated circuit for MAC (Multiplexed Analog Component) TV standard is described. The chip performs the recovery of a system clock from a digitally encoded voice signal, clamping of a video signal for DC-level restoration, and precise gain control of a video signal in the presence of a large amplitude variation. A PLL (Phase Locked Loop) is used for timing recovery and a new gain control circuit is proposed which enhances its accuracy and dynamic range by employing two identical four-quadrant analog multipliers. The chip is designed in full custom with 1.5um BiCMOS technology, and layout verification is completed by post-simulation with the extracted circuit.

• 전자공학회논문지B
• /
• 제31B권9호
• /
• pp.67-75
• /
• 1994

In this paper, we manufactured the continuum receiver system for observing the continuum waves emitted from the continuum sources with using the 14m radio-telescope. The receiving system measures the total power of the continuum sources and consists of DC-amplifier, beam-chopper system. Phase-Locked Loop(PLL) circuit, blanking circuit and its period selection circuit, V/F converter, and counter part which are capable of interfacing with the computer which is used for a data acquisition and making the radio-telescope track the source. We compared the obsevation results which use the existing DVM method with the observation results which use the continuum receiver to measure the total power of the sources. Moreover, by method of beam switching observation which uses newly installed beam chopper system. We can significantly improve the observational efficiency more than the existing position switching observation method.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.353-356
• /
• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• 한국군사과학기술학회지
• /
• 제8권4호
• /
• pp.102-109
• /
• 2005

In this paper, we propose a new listen-in technique to overcome the problems and the shortcomings which could possibly meet in the previous listen-in methods to deal with the blind signal manually according to operator's decision. In the proposed listen-in method, receiving the signals, classifying the modulation types, and demodulating the signals can be done automatically without operator's intervention. We realize the listen-in technology by developing the high speed frequency tuner, the automatic modulation recognizer, and the signal demodulator. In conclusion, we confirm and show that the developed equipment has a good performance in classifying the modulation type through the computer simulation and the field test.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
• /
• pp.1018-1023
• /
• 1998

This paper presents an effective control scheme incorporated in the voltage-fed half-bridge series resonant inverter for induction heating applications, which is based upon a load-adaptive tuned frequency tracking control strategy using PLL(Phase Locked Loop) and its peripheral control circuit. The proposed control strategy ensures a stable operation characteristics of overall inverter system and ZVS(Zero Voltage Switching0 operation in spite of sensitive load parameters variation as well as power regulation, specially in the non-magnetic heating loads. The simulation results and the performance characteristics in the steady-state are shown as compared with the experimental results for a prototype induction cooking system rated at 1.2kW.