A process and temperature compensated 400 MHz Frequency Synthesizer

공정과 온도 보상된 400 MHz 주파수합성기

One of the major reasons for not integrating a VCO on one-chip in a PLL (phase locked loop) system is the large chip-to-chip variation of the VCO (voltage controlled oscillator) center frequency. In this thesis, a simple bias technique is proposed to compensate the process fluctuation. The proposed bias technique is applied to the VCO and it reduces the deviation of the VCO center frequency from 35% to 8 %. With the suggested bias technique, a 400 MHz frequency synthesizer is designed for general purpose. It utilizes a programmable divider for various division ratio. The design methodology provides the possibility of the one-chip solution for a PLL system.