• Proceedings of the KIPE Conference
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• 2007.11a
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• pp.190-192
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• 2007

본 논문에서는 새로운 FFT에 의한 계통위상 추정 알고리즘을 제안한다. 신재생 에너지 분야에 적용되는 계통연계형 인버터에서는 계통과 동기를 위해서는 반드시 계통의 위상 정보가 필요하다. 일반적으로 사용하는 3상 D-Q 변환에 의한 위상 추종과 달리 새롭게 제안하는 FFT를 사용하는 알고리즘은 게인 튜닝 부분이 없으며 FFT의 특성상 기본주파수 이외의 성분을 제외한 강력한 노이즈 제거효과로 인해 직접적이며 노이즈에 강한 특징을 가지고 있다. 시뮬레이션과 실험을 통하여 제안한 알고리즘의 성능이 만족할 만한 성능을 얻을 수 있음을 보였다.

• Proceedings of the KIPE Conference
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• 2011.07a
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• pp.471-472
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• 2011

본 논문에서는 상 절체와 같은 급작스러운 위상천위 발생시에도 위상추정에 의한 계통연계를 위한 고속 PLL 알고리즘을 제안하였다. 제안된 고속 PLL 알고리즘은 2상 정지좌표계에서 취득한 위상정보의 불안정성을 보상하기 위함으로 저주파 필터를 이용한 정지좌표계상의 위상정보를 feed-forward로 사용한 결과, 외란에 강인한 위상각을 추정하는 알고리즘을 구현하였으며, PSIM을 이용한 시뮬레이션을 통하여 제안한 알고리즘의 타당성을 검증하였다.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1185-1187
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• 1992

In this paper, PWM control is applied to the microprcessor-based adjustable speed dc motor drives. The motor drive system is composed of phase locked loop. Main drive circuit of the system is consisted of H-type bridge with switching transistors. PWM drive circuit is linearized by adding flywheeling diodes. And also. We study the optimum PWM data and period time so that it hase a nearly liner relationship between current and torque.

• Journal of the Korea Institute of Military Science and Technology
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• v.9 no.3
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• pp.116-122
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• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.778-782
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• 2004

본 논문에서는 전력 품질 기기의 제어에 있어서 필수적 요소라고 할 수 있는 전원각을 찾는 방법중에서 PLL(Phase Locked Loop)에 관하여 기존의 방식들을 먼저 알아보고, 정상분을 추출하여 이용하는 기존의 PLL 방식을 무정전전원장치에 적합한 형태로 개선한 주파수를 제한한 PLL 방식을 제안하였다. 제안된 PLL 방식은 기존의 PI 제어기에 주파수 제한기(limiter)와 안티 와인드업(anti-windup)을 추가하였다. 이것의 기본적인 동작 원리는 기존의 방법들과 같지만, 차이점은 주파수 제한기의 삽입으로 인하여 주파수 변동률을 일정한 범위 내에서 제한할 수 있다는 것이다. 기존의 PLL 방법과 본 논문에서 제안된 주파수를 제한한 PLL 방법의 차이를 알아보기 위하여 동적 전압 보상기로 전압을 보상하는 시뮬레이션을 하였고, 결과적으로 제안된 주파수를 제한한 PLL 방법이 기존의 PLL 방법보다 UPS에 적합함을 입증하였다.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.985-987
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• 2004

Switched Reluctance Motor(SRM) drive system is known to provide good torque characteristics and high efficiency drive. However, speed variation caused by higher torque ripple is one of main drawback. The Phase-Locked Loop (PLL) technique in conjunction with dynamic dwell angle control has good speed regulation characteristics. In this paper, appropriate advance angle control for high efficiency drive and PLL technique for accurate speed control is proposed. A TMS320F240 DSP is used to realize this drive system. Test results show that the system has good dynamic and precise speed control ability as well as high efficiency.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.967-971
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• 2004

The switched reluctance drive is known to provide good adjustable speed characteristics with high efficiency. However, higher torque ripple and lack of the precise speed control are drawbacks. In the paper, a PLL(Phase Locked Loop) technique is adopted to regulate the dwell angle instantaneously. A PLL control technique in conjunction with dynamic dwell angle control scheme has good speed regulation characteristics. The F240 DSP based control system is used to realize this drive system. Test results show that the system has the ability to achieve good dynamic and precise speed control.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.874-877
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• 1987

In this paper a DPLL circuit realizable by digital IC's is propose and the principles of general DPLL are described. An all Digital phase locked loop is designed, analyzed, and tested. In particular, the approach of invoking Gaussian assumption on the decision variable and based on S.O.Rices theory is used. As a performance of the above PLL detector operating on low data rate FSK is given and demonsrtated to be FSK reception.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.115-122
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• 1996

A 300MHz PLL including FVC (frequency to voltage converter) is designed and fabricated in 0.8$\mu$m CMOS process. In this design, a FVC and a 2nd - order passive filter are added to the conventional charge-pump PLL to improve the acquisition time. The dual-rijng VCO(voltage controlled oscillator) realized in this paper has a frequency range form 208 to 320MHz. Integrated circuits have been fully tested and analyzed in detail and it is proved that pull-in speed is enhanced with the use fo FVC. In VCO range from 230MHz to 310MHz, experimental results show that realized PLL exhibits 4 times faster pull-in speed than that of conventional PLL.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.28-34
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• 1986

The frequency synthesizer for Fast Frequency Hopping System musy be capable of a fast tuning with a small step frequency over wide band. The most conventional frequency synthesizer that uses the phase locked loop (PLL) enables the wide band problem but have a poor side of the low resolution and the transient response. In this paper, we have discussed the experimental results of a direct digital frequency synthesizer which can be applicable to the Fast Frequency Hopping System, using digital-to-analoq (D/A)conversion techniques. With this system we can find the merits of a fine resolution and the possibility of a fast tuning leaving the problems of transent frequency.