• BMB Reports
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• v.46 no.8
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• pp.391-397
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• 2013

The ATP-inhibited Plant Mitochondrial $K^+$ Channel ($PmitoK_{ATP}$) was discovered about fifteen years ago in Durum Wheat Mitochondria (DWM). $PmitoK_{ATP}$ catalyses the electrophoretic $K^+$ uniport through the inner mitochondrial membrane; moreover, the co-operation between $PmitoK_{ATP}$ and $K^+/H^+$ antiporter allows such a great operation of a $K^+$ cycle to collapse mitochondrial membrane potential (${\Delta}{\Psi}$) and ${\Delta}pH$, thus impairing protonmotive force (${\Delta}p$). A possible physiological role of such ${\Delta}{\Psi}$ control is the restriction of harmful reactive oxygen species (ROS) production under environmental/oxidative stress conditions. Interestingly, DWM lacking ${\Delta}p$ were found to be nevertheless fully coupled and able to regularly accomplish ATP synthesis; this unexpected behaviour makes necessary to recast in some way the classical chemiosmotic model. In the whole, $PmitoK_{ATP}$ may oppose to large scale ROS production by lowering ${\Delta}{\Psi}$ under environmental/oxidative stress, but, when stress is moderate, this occurs without impairing ATP synthesis in a crucial moment for cell and mitochondrial bioenergetics.

• Journal of computational fluids engineering
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• v.10 no.2
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• pp.1-6
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• 2005

The HANARO, a multi-purpose research reactor of 30 MWth, open-tank-in-pool type, has been under normal operation since its initial criticality in February, 1995. The HANARO is composed af inlet plenum, grid plate, core channel with flow tubes and chimney. The reactor core channel is located at about twelve meters (12 m) depth of the reactor pool and cooled by the upward flow that the coolant enters the lower inlet of the plenum, rises up through the grid plate and the core channel and comes out from the outlet of chimney. A fission moly guide tube is extended from the reactor core to the top of the reactor chimney for easily loading a fission moly target under the reactor normal operation. But active coolant through the core can be quickly raised up to the top of the chimney through the guide tube by jet flow. This paper describes an analytical analysis that is the study of the flow behavior through the guide tube under reactor normal operation and unloading the target. As results, it was conformed through the analysis results that the flow rate, reduced to about fourteen kilogram per second (14 kg/s) from the original flow rate of sixteen point three kilogram per second (16.3 kg/s) did not show the guide tube jet.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.6
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• pp.759-766
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• 2018

Although the Act on the Prevention of Light Pollution Due to Artificial Lighting has been enforced since 2013, the area of advertisement lighting has made slow progress in solving the problems of light pollution. This paper first investigated institutional problems by analyzing domestic laws and regulations relating to the light pollution of advertisement lighting, and investigated and analyzed methods for reducing light pollution that were applied in overseas countries. Then, problems of light pollution were analyzed by conducting a research on the actual status of advertisement lightings installed in South Korea and applying various methods for reducing light pollution, and advertisement lighting using LED was recommended. As a method for reducing light pollution that can be applied to the process of manufacturing channel letter-type advertisement lights, power consumption per unit area ($W/m^2$) was proposed, and $100W/m^2$ was recommended as a value currently suitable for South Korea.

• ETRI Journal
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• v.42 no.6
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.195-198
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• 2000

This paper have been analyzed performance of DS-CDMA/QPSK system in short range IVC, and evaluated packet uu rate(PER) in an On-Ray Rician channel model suitable for platoon driving of AVHS that 60GHz millimeter wave is very powerful to MP(multipath-wave). We analyzed probability characteristic of system as variation of Rician factor and user number in One-Ray Rician fading environment and evaluated packet error rate(PER) according to inter-vehicle distance when the BCH channel coding(255,247,1) and diversity schemes is adopted.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.9
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• pp.2086-2097
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• 2012

A terminal-based dynamic clustering algorithm is proposed in a multi-cell scenario, where the user could select the cooperative BSs from the predetermined static base stations (BSs) set based on dynamic channel condition. First, the user transmission rate is derived based on linear precoding and per-cell feedback scheme. Then, the dynamic clustering algorithm can be implemented based on two criteria: (a) the transmission rate should meet the user requirement for quality of service (QoS); (b) the rate increment exceeds the predetermined constant threshold. By adopting random vector quantization (RVQ), the optimized number of cooperative BSs and the corresponding channel conditions are presented respectively. Numerical results are given and show that the performance of the proposed method can improve the system resources utilization effectively.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.4 no.6
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• pp.1116-1132
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• 2010

In this paper, a new forward error correction (FEC) protocol is proposed for point-to-multipoint satellite links. Link-layer error control protocols in point-to-multipoint satellite links impose several problems such as unreliability and receiver-heterogeneity. To resolve the problem of heterogeneous error rates at different receivers, the proposed scheme exploits multiple multicast channels to which each receiver tunes. The more channels a receiver tunes to, the more powerful error correcting capability it achieves. Based on its own channel condition, each receiver tunes to as many channels as it needs, which prevents from receiving unwanted parities. Furthermore, each receiver saves the decoding time, processing overhead, and processing energy. Performance evaluation shows that the proposed scheme guarantees the target PER while saving energy. The proposed technique is highly adaptive to the channel variation with respect to the throughput efficiency, and provides scalable PER and throughput efficiency.

• ETRI Journal
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• v.29 no.1
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• pp.79-88
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• 2007

This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.1
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• pp.33-38
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• 2017

In this paper, a 4-channel common-cathode VCSEL diode driver array with 3.125 Gb/s per channel operation speed is realized. In order to achieve faster speed of the switching main driver with relatively large transistors, the transmitter array chip consists of a pre-amplifier with active inductor stage and also an input buffer with modified equalizer, which leads to bandwidth extension and reduced current consumption. The utilized VCSEL diode provides inherently 2.2 V forward bias voltage, $50{\Omega}$ resistance, and 850 fF capacitance. In addition, the main driver based upon current steering technique is designed, so that two individual current sources can provide bias currents of 3.0 mA and modulation currents of 3.3 mA to VCSEL diodes. The proposed 4-channel VCSEL driver array has been implemented by using a $0.11-{\mu}m$ CMOS technology, and the chip core occupies the area of $0.15{\times}0.18{\mu}m^2$ and dissipates 22.3 mW per channel.