• 제목/요약/키워드: Path switch

검색결과 131건 처리시간 0.035초

Robust $H_8$State Feedback Congestion Control of ATM for linear discrete-time systems with Uncertain Time-Variant Delay

  • Kang, Lae-Chung;Kim, Young-Joong;Lim, Myo-Taeg
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2004년도 ICCAS
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    • pp.1758-1763
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    • 2004
  • This paper focuses on congestion control for ATM network with uncertain time-variant delays. The time-variant delays can be distinguished into two distinct components. The first one is represented by time-variant queueing delays in the intermediate switches that are occurred in the return paths of RM cells. The next one is a forward path delay. It is solved by the VBR model which quantifies the data propagation from the sources to the switch. Robust $H_8$ control is studied for solving congestion problem with norm-bounded time-varying uncertain parameters. The suitable robust $H_8$ controller is obtained from the solution of a convex optimization problem through LMI technique.

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Flying Capacitor Snubber를 적용한 PFC(Power Factor Correction) Boost 컨버터에 관한 연구 (A Study on the PFC(Power Factor Correction) boost converter applied Flying Capacitor Snubber.)

  • 김병철;이희승;서재호
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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    • pp.77-80
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    • 2003
  • Switching Mode Power Supply(SMPS) is widely used in many industrial fields. Power factor improvement and harmonic reduction technique are very important in SMPS. In this paper, we propose the circuit applied Flying Capacitor Snubber for improving power factor of boost converter on fast switching state. Snubber circuit consists of a inductor, two diodes and a capacitor. The losses of switching are reduced by inserting a snubber inductor in the series path of the boost switch and the rectifier diode to control the di/dt rate of the rectifier during it's turn-off. Prior to actual experiment, the circuit analysis Is implemented by PSPICE simulation.

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A New Zero Voltage Transition Bridgeless PFC with Reduced Conduction Losses

  • Mahdavi, Mohammad;Farzanehfard, Hosein
    • Journal of Power Electronics
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    • 제9권5호
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    • pp.708-717
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    • 2009
  • In this paper a new zero voltage transition PWM bridgeless PFC is introduced. The auxiliary circuit provides soft switching condition for all semiconductor devices. Also, in the resonant path of the auxiliary circuit, only two semiconductor devices exist. Therefore the resonant conduction losses are low. Furthermore, the auxiliary circuit semiconductor elements consist of only one diode and one switch. The proposed auxiliary circuit is applied to a bridgeless PFC converter to further reduce conduction and switching losses. In this paper, the operating modes of this converter are explained and the resulting ideal and simulation waveforms are shown. The presented experimental results justify the theoretical analysis.

M4 Interface를 지원하는 ATM 네트워크 관리 시스템에 관한 연구 (A Study on ATM Network Management System Supporting M4 Interface)

  • 이범;최영수;정진욱
    • 한국정보처리학회논문지
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    • 제6권11S호
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    • pp.3367-3378
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    • 1999
  • ATM technology, which acts as a representative high-speed bandwidth technology, plays an important role in Internet environment. ATM network, supporting QoS(Quality of Service) and various traffic characters in high speed, configures many VPC(Virtual Path Connection)/VCC(Virtual Channel Connection). It is important to guarantee the QoS of each connection and it is necessary for the network manager to search element affecting the QoS of VPC/VCC and to control ATM network correctly. In the paper, the management information of VPC/VCC, that ATM network manager Using the fault notification for ATM switch, we can manage the configuration, fault and performance of ATM network. Thus, we extracted the configuration, fault and performance monitoring item from the ATM-MIB and SNMP M4 Network Element View MIB. And we designed the ATM network configuration, fault and performance management system based on the extracted item.

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A New Cascaded Multilevel Inverter Topology with Voltage Sources Arranged in Matrix Structure

  • Thamizharasan, S.;Baskaran, J.;Ramkumar, S.
    • Journal of Electrical Engineering and Technology
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    • 제10권4호
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    • pp.1552-1557
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    • 2015
  • The paper unleashes a new idea to arrive at reduced switch count topological structures configured in the form of a matrix for a cascaded Multi level inverter (CMLI). The theory encircles to minimize the number of switches involved in the conduction path and there from acclaim reduced input current distortion, lower switching losses and electromagnetic interference. The focus extends to standardize the number of power devices required for reaching different levels of output voltage from the same architecture. It includes appropriate pulse width modulation (PWM) strategy to generate firing pulses and ensure the desired operation of the power modules. The investigative study carries with it MATLAB based simulation and experimental results obtained using suitable prototypes to illustrate the viability of the proposed concept. The promising nature of the performance projects a new dimension in the use of single phase MLIs for renewable energy related applications.

배전자동화 시스템에서 전력설비 부하균등화를 고려한 피더간 연계점 최적위치선정 (A Method for Optimal Location of Feeder Tie Switches for Improving Equal Load of Electric Power Equipment in Distribution Automation System)

  • 임일형;임성일;최면송;이승재;신창훈;하복남
    • 전기학회논문지
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    • 제56권5호
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    • pp.821-828
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    • 2007
  • This paper proposes a new algorithm to find optimal location of open switches connecting feeders in distribuion system. In order to enhance power system reliability by minimizing outage area in case of fault, the load balance among the facilities such as transformers and feeders is considered to optimize. The combination of optimal position of normal open switches can be found by moving tie along the direct path connecting two feeders related to the open switch while the whole optimization problem is separated into many small problems. The proposed algorithm is shown by case study results that, it is simple and takes short calculation time to apply to the DAS (Distribution Automation System) in KEPCO (Korea Electric Power Cooperation).

다중 영역 OSPF 설정에 대한 연구 (A Study on MultiArea OSPF Configuration)

  • 김동주;소계원;노철우
    • 한국콘텐츠학회:학술대회논문집
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    • 한국콘텐츠학회 2015년도 춘계 종합학술대회 논문집
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    • pp.31-32
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    • 2015
  • 본 논문에서는 컴퓨터 망에서 동적라우팅 프로토콜로 다중영역을 지원하는 OSPF (Open Shortest Path First)를 중심으로 망 축약(summary), 타 프로톨과의 연동을 위한 재분배(redistribution), Virtual Link 등 복잡한 설정 기법을 연구하고 이를 신라대학교 LAN 구성에 적용한다. 시스코의 망 시뮬레이터 장비인 패킷트레이서를 활용하여 라우터와 스위치는 각각 2620XM Router, 2950T-24 Switch를 사용하고, 라우팅 프로토콜은 OSPF, EIGRP(Enhanced Interior Gateway Routing Protocol)를, 또한 이들 간의 연결을 위해서는 재분배를 이용하고, 다중 영역 중 백본 area에 인접하지 않는 area에 대한 연결을 위해서는 Virtual Link 등 여러 설정 기법을 사용한다. 전체 망 구성 연결 후에는 이들 설정에 대한 통신상태를 확인한다.

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버퍼의 점유도에 기초한 입력버퍼 ATM 스위치의 경합제어 방식 (A contention resolution scheme based on the buffer occupancy for th einput-buffer ATM switch)

  • 백정훈;박제택
    • 전자공학회논문지S
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    • 제34S권1호
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    • pp.36-42
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    • 1997
  • This paper proposes a high-speed contention resolution scheme featuring high flexibility to the bursty traffic for an input buffering ATM switching architecture and its hardware strategy. The scheme is based on the threshold on the occupancy of the input buffer. As the proposed scheme utilizes the threshold, it has high flexibility to the fluctuations of the input traffic. The hardware strategy for the proposed policy is provided with the aim of the simple structure that achieves the reduction of the signal path and the power consumption. The performance on the average buffer size of the proposed policy is performed and compared with the conventional schame under the bursty traffic through both the analysis based on the markov hain and the simulation. The relations among the parameters on the proposed policy is analyzed to improve the performance.

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시간지연을 고려한 ATM 망에서의 체증제어를 위한 $H_{\infty}$ 제어기 설계 (Robust $H_{\infty}$ State Feed back Congestion Contro1 of ATM for lineardiscrete-time systems with Uncertain Time-Variant Delav)

  • 강래청;정우채;김영중;임묘택
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2004년도 하계학술대회 논문집 D
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    • pp.2161-2163
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    • 2004
  • This paper focuses on congestion control for ATM network with uncertain time-variant delays. The time-variant delays can be distinguished into two distinct components. The first one that is represented by time-variant queueing delays in the intermediate switches is occurred in the return paths of RM cells. The next one is a forward path delay. It is solved by the VBR Model which quantifies the data propagation from the sources to the switch. Robust $H_{\infty}$ control is studied for solving congestion problem with norm-bounded time-varying uncertain parameters. The suitable robust $H_{\infty}$ controller is obtained from the solution of a convex optimization problem including terms of LMIs.

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LPF 내장형 7중 대역 LTCC 프런트엔드모듈 설계 (Design of 7 Bands LTCC Front-end Module Embedded LPF)

  • 김형은;서영광;김인배;문제도;이문규
    • 전기학회논문지
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    • 제61권3호
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    • pp.427-432
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    • 2012
  • In this paper, we have designed and fabricated 7-bands (GSM 850/900, DCS/PCS, and UMTS 3 bands) LTCC front end module (FEM) embedded LPF (low pass filter) to efficiently eliminate harmonics generated in TX path. The proposed FEM is composed of flip-chip typed CMOS SP9T switch to select transceiver signals, dual type SAW filters to receive Rx signals, and 0603 size chip components for the antenna matching and ESD protection. The whole size of FEM is $4.5{\times}3.2{\times}1.2mm^3$. The insertion loss of Tx and Rx ports are measured at 1.7 dB and 4.8 dB, respectively.