• Title/Summary/Keyword: Parity check

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Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory Relocation (연산기와 메모리 재사용을 이용한 효율적인 DVB-S2 규격의 LDPC 복호기 구조)

  • Park Jae-Geun;Lee Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.9 s.351
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    • pp.31-37
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    • 2006
  • Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

A performance analysis of layered LDPC decoder for mobile WiMAX system (모바일 WiMAX용 layered LDPC 복호기의 성능분석)

  • Kim, Eun-Suk;Kim, Hae-Ju;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.4
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    • pp.921-929
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    • 2011
  • This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

Protograph-Based Block LDPC Code Design for Marine Satellite Communications (해양 위성 통신을 위한 프로토그래프 기반 블록 저밀도 패리티 검사 부호 설계)

  • Jeon, Ki Jun;Ko, Byung Hoon;Myung, Se-Chang;Lee, Seong Ro;Kim, Kwang Soon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.39C no.7
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    • pp.515-520
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    • 2014
  • In this paper, the protograph-based block low density parity check (LDPC) code, which improves the performance and reduces the encoder/decoder complexity than the conventional Digital Video Broadcasting Satellite Second Generation (DVB-S2) LDPC code used for the marine satellite communication, is proposed. The computer simulation results verify that the proposed protograph-based LDPC code has the better performance in both the bit error rate (BER) and the frame error rate (FER) than the conventional DVB-S2 LDPC code. Furthermore, by analyzing the encoding and decoding computational complexity, we show that the protograph-based block LDPC code has the efficient encoder/decoder structure.

UEP Effect Analysis of LDPC Codes for High-Quality Communication Systems (고품질 통신 시스템을 위한 LDPC 부호의 UEP 성능 분석)

  • Yu, Seog Kun;Joo, Eon Kyeong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.6
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    • pp.471-478
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    • 2013
  • Powerful error control and increase in the number of bits per symbol should be provided for future high-quality communication systems. Each message bit may have different importance in multimedia data. Hence, UEP(unequal error protection) may be more efficient than EEP(equal error protection) in such cases. And the LDPC(low-density parity-check) code shows near Shannon limit error correcting performance. Therefore, the effect of UEP with LDPC codes is analyzed for high-quality message data in this paper. The relationship among MSE(mean square error), BER(bit error rate) and the number of bits per symbol is analyzed theoretically. Then, total message bits in a symbol are classified into two groups according to importance to prove the relationship by simulation. And the UEP performance is obtained by simulation according to the number of message bits in each group with the constraint of a fixed total code rate and codeword length. As results, the effect of UEP with the LDPC codes is analyzed by MSE according to the number of bits per symbol, the ratio of the message bits, and protection level of the classified groups.

Design and Performance Evaluation of Improved Turbo Equalizer (개선된 터보 등화기의 설계와 성능 평가)

  • An, Changyoung;Ryu, Heung-Gyoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.8
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    • pp.28-38
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    • 2013
  • In this paper, we propose a improved turbo equalizer which generates a feedback signal through a simple calculation to improve performance in single carrier system with the LMS(least mean square) algorithm based equalizer and LDPC(low density parity check) codes. LDPC codes can approach the Shannon limit performance closely. However, computational complexity of LDPC codes is greatly increased by increasing the repetition of the LDPC codes and using a long parity check matrix in harsh environments. Turbo equalization based on LDPC code is used for improvement of system performance. In this system, there is a disadvantage of very large amount of computation due to the increase of the repetition number. To less down the amount of this complicated calculation, The proposed improved turbo equalizer adjusts the adoptive equalizer after the soft decision and the LDPC code. Through the simulation results, it's confirmed that performance of improved turbo equalizer is close to the SISO-MMSE(soft input soft output minimum mean square error) turbo equalizer based on LDPC code with the smaller amount of calculation.

Structured LDPC Codes for Mobile Multimedia Communication Systems (이동 멀티미디어 통신 시스템을 위한 구조적인 저밀도패리티검사 부호)

  • Yu, Seog-Kun;Joo, Eon-Kyeong
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.48 no.2
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    • pp.35-39
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    • 2011
  • Error correcting codes with easy variability in code rate and codeword length in addition to powerful error correcting capability are required for present and future mobile multimedia communication systems. And low complexity is also needed for the compact mobile terminals. In general, the irregular random LDPC(low-density parity-check) code is known to have the superior performance among various LDPC codes. But it has inefficiency since the various parity check matrices for various services should be stored for encoding and decoding. The structured LDPC codes which can easily provide various rates and lengths are studied recently. Therefore, the flexibility, memory size, and error performance of various structured LDPC codes are compared and analyzed in this paper. And the most appropriate structured LDPC code is also suggested.

An Improved Decoding Scheme of LCPC Codes (LCPC 부호의 개선된 복호 방식)

  • Cheong, Ho-Young
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.11 no.4
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    • pp.430-435
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    • 2018
  • In this paper, an improved decoding scheme for low-complexity parity-check(LCPC) code with small code length is proposed. The LCPC code is less complex than the turbo code or low density parity check(LDPC) code and requires less memory, making it suitable for communication between internet-of-things(IoT) devices. The IoT devices are required to have low complexity due to limited energy and have a low end-to-end delay time. In addition, since the packet length to be transmitted is small and the signal processing capability of the IoT terminal is small, the LCPC coding system should be as simple as possible. The LCPC code can correct all single errors and correct some of the two errors. In this paper, the proposed decoding scheme improves the bit error rate(BER) performance without increasing the complexity by correcting both errors using the soft value of the modulator output stage. As a result of the simulation using the proposed decoding scheme, the code gain of about 1.1 [dB] was obtained at the bit error rate of $10^{-5}$ compared with the existing decoding method.

Effect of Processing Gain on the Iterative Decoding for a Recursive Single Parity Check Product Code (재귀적 SPCPC에 반복적 복호법을 적용할 때 처리 이득이 성능에 미치는 영향)

  • Chon, Su-Won;Kim, Yong-Cheol
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.9C
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    • pp.721-728
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    • 2010
  • CAMC (constant amplitude multi-code) has a better performance of error correction in iterative decoding than SPCPC (single parity check product code). CAMC benefits from a processing gain since it belongs to a spread spectrum signal. We show that the processing gain enhances the performance of CAMC. Additional correction of bit errors is achieved in the de-spreading of iteratively decoded signal. If the number of errors which survived the iterative decoding is less than or equal to ($\sqrt{N}/2-1$), all of the bit errors are removed after the de-spreading. We also propose a stopping criterion in the iterative decoding, which is based on the histogram of EI (extrinsic information). The initial values of EI are randomly distributed, and then they converge to ($-E_{max}$) or ($+E_{max}$) over the iterations. The strength of the convergence reflects how successfully error correction process is performed. Experimental results show that the proposed method achieves a gain of 0.2 dB in Eb/No.

Row-splitting Algorithm for Low Density Parity Check Codes (LDPC 부호를 위한 행 분할 알고리즘)

  • Jung, Man-Ho;Lee, Jong-Hoon;Kim, Soo-Young;Song, Sang-Seob
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.45 no.2
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    • pp.92-96
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    • 2008
  • Practical communication systems need to operate at various different rates. This paper describes and analyzes low-density parity check codes for various different rates. From a specific mother code, it allows LDPC codes for different rate. The advantage of this technique is that each different rate LDPC codes have a same block length as mother code though the rate changes so it can make up for the weak points of puncturing and shortening which reduce their block length as the rate changes. Row-splitting method is to split the row, so that the rate changes from a higher rate to lower rate and cause of its own property, it can overcome the defect of row-combining method.

Efficient Partial Parallel Encoders for IRA Codes in DVB-S2 (DVB-S2 IRA Code를 위한 최적 부호화 방법)

  • Hwang, Sung-Oh;Lee, Jai-Yong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.11C
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    • pp.901-906
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    • 2010
  • Low density parity check (LDPC) code, first introduced by Gallager and re-discovered by MacKay et al, has attracted researcher's interest mainly due to their performance and low decoding complexity. It was remarkable that the performance is very close to Shannon capacity limit under the assumption of having long codeword length and iterative decoder. However, comparing to turbo codes widely used in the current mobile communication, the encoding complexity of LDPC codes has been regarded as the drawback. This paper proposes a solution for DVB-S2 LDPC encoder to reduce the encoder latency. We use the fast IRA encoder that use the transformation of the parity check matrix into block-wise form and the partial parallel process to reduce the number of system clocks for the IRA code encoding. We compare the proposed encoder with the current DVB-S2 encoder to show that the performance of proposal is better than that of the current DVB-S2 encoder.