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Architecture of an LDPC Decoder for DVB-S2 using reuse Technique of processing units and Memory Relocation  

Park Jae-Geun (Dept. of Electronic Engr., Soongsil University)
Lee Chan-Ho (School of Electronic Engr., Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.9, 2006 , pp. 31-37 More about this Journal
Abstract
Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.
Keywords
LDPC code; semi-random; Hybrid H-matrix; partly parallel structure; DVB-S2;
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