• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제15권1호
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• pp.51-58
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• 2001

Recently, DC-DC converters significantly increase the total losses as rising switching frequency. Trnditional soft switching technique for reducing switching losses even increase voltage/Clment stress of switch In this paper, Resonant circuit for soft switching is connected in parallel with power stage and only operates just before tum-on of the main sWItch. Therefore, ills doesn't affect the total circuit QI'||'&'||'pound;ration. The object of tIns paper is to make the linearized equivalent loss mxleIs. and to analyze the total losses by experiment. ZVT-PWlvI converter designed with 170-260[V] input, 400[V] 5[A] output, and 100[kHz] switching frequency is tested respectively with 500[W], 1[kW], 1.5[kW], and 2[kW] loads. The total losses in input 220[V], 2[kW] load are analyzed by usirm the linearized equivalent loss models.

• The Transactions of the Korean Institute of Power Electronics
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• 제16권3호
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• pp.242-249
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• 2011

The proposed converter has easy device selection for high step-up and high power applications since boost half bridge and voltage doubler cells are connected, respectively, in parallel and series in order to increase output power and voltage. Especially, optimized design of high frequency transformers is possible owing to reduced turn ratio and eliminated dc offset, and distributed power through three cores is beneficial to low profile and thermal distribution. The proposed converter does not necessitate start-up circuit and additional clamp circuit due to the use of whole duty range between 0 and 1 and is suitable for applications with wide input voltage range. Also, high efficiency can be achieved since ZVS turn on of switches are achieved in wide duty cycle range and ZCS turn on and off of diodes are achieved. The proposed converter was validated through 5 kW prototype.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제17권5호
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• pp.269-274
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• 2016

This paper proposes the development of a low frequency electronic hammer drive system that is used to prevent scaling or clogging in the hopper process. The electro-mechanical hammering driving method involves the generation of vibration and impact energy. The operation principles of the electromagnetic hammer were considered by parallel/series spring coefficient analysis and the amount of kinetic energy generated was calculated from the product of the equivalent spring constant, which is coupled with the E core and the gap of between the E core and I core. In addition, the Pulsation Driving algorithm was applied to the proposed electromagnetic hammer to obtain the maximizing kinetic energy. This algorithm was then implemented by a logical AND operation process and micro-controller (atmega128) built in functions with a timer interrupt and PWM generation function. The driving circuit of the electromagnetic hammer was designed using the H-bridge type IGBT circuit. The experimental test was performed by usefulness of the developed electromagnetic hammer systems with the acceleration measurement method. The experimental result showed that the proposed system has good kinetic energy generation performance and can be applied to the hopper process.

• Journal of the Korea Institute of Information and Communication Engineering
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• 제12권6호
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• pp.1056-1063
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• 2008

This paper describes an efficient design of a multi-standard Viterbi decoder that supports multiple constraint lengths and code rates. The Viterbi decoder is parameterized for the code rates 1/2, 1/3 and constraint lengths 7,9, thus it has four operation nodes. In order to achieve low hardware complexity and low power, an efficient architecture based on hardware sharing techniques is devised. Also, the optimization of ACCS (Accumulate-Subtract) circuit for the one-point trace-back algorithm reduces its area by about 35% compared to the full parallel ACCS circuit. The parameterized Viterbi decoder core has 79,818 gates and 25,600 bits memory, and the estimated throughput is about 105 Mbps at 70 MHz clock frequency. Also, the simulation results for BER (Bit Error Rate) performance show that the Viterbi decoder has BER of $10^{-4}$ at $E_b/N_o$ of 3.6 dB when it operates with code rate 1/3 and constraints 7.

• Journal of Magnetics
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• 제10권3호
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• pp.122-127
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• 2005

New classes of LC resonators for micro magnetic sensor device were proposed and fabricated. The first type LC resonator (Type I) consists of a small piece of microwire and two cylindrical electrodes at the end of the microwire without direct contact to its ferromagnetic core. In type I resonator the ferromagnetic core of the microwire and cylindrical electrodes act as an inductor and two capacitors respectively to form a LC circuit. The second type LC resonator (Type II) consists of a solenoidal micro-inductor with a bundle of soft magnetic microwires as a core. The solenoidal micro-inductors fabricated by MEMS technique were $500\sim1,000\;\mu{m}$ in length with $10\sim20$ turns. A capacitor is connected in parallel to the micro-inductor to form a LC circuit. A tiny glass coated $CO_{83.2}B_{3.3}Si_{5.9}Mn_{7.6}$ microwire was fabricated by a glass-coated melt spinning technique. A supergiant magneto-impedance effect was found in a type I resonator as much as 400,000% by precise tuning frequency at around 518.51 MHz. In type II resonator the changes of inductance as a function of external magnetic field in micro-inductors with properly annealed microwire cores were varied as much as 370%. The phase angle between current and voltage was also strongly dependent on the magnetic field. The drastic increments of magnetoimpedance at near the resonance frequency were observed in both types of LC resonators. Accordingly, the sudden change of the phase angle, as large as $180^{\circ}C$, evidenced the occurrence of the resonance at a given external magnetic field.

• Journal of Advanced Navigation Technology
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• 제25권3호
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• pp.229-235
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• 2021

This paper proposes a method of implementing an unequal power divider for high splitting ratios by using transmission lines connected with open and short stubs. The proposed method is an equivalent circuit analysis of a transmission line with an additional port so that it can be converted to an arbitrary impedance in the center of a 2-port transmission line and a 3-port transmission line with an open or short stub connected in parallel to each port. To prove the validity of this method, a Wilkinson power divider with k² = 20 dB splitting ratio and a Gysel power divider with k² = 17 dB splitting ratio were designed at a center frequency of 1 GHz using a 3-port transmission line equivalent circuit. The experimental results of the electrical characteristics are in good agreement with the simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제39권11호
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• pp.24-32
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• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제47권1호
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• pp.60-68
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• 2010

In case of sensorineural hearing loss, auditory perception can be activated by electrical stimulation of the nervous system via electrode implanted into the cochlea or auditory nerve. Since the tonotopic map of the human auditory nerve has not been definitively identified, the recording of auditory nerve signal with microelectrode is desirable for determining the tonotopic map. This paper proposes the multi-channel analog front-end for auditory nerve signal detection. A channel of the proposed analog front-end consists of an AC coupling circuit, a low-power 4th-order Gm-C LPF, and a single-slope ADC. The AC coupling circuit transfers only AC signal while it blocks DC signal level. Considering the bandwidth of the auditory signal, the Gm-C LPF is designed with OTAs adopting floating-gate technique. For the channel-parallel ADC structure, the single-slope ADC is used because it occupies the small silicon area. Experimental results shows that the AC coupling circuit and LPF have the bandwidth of 100 Hz - 6.95 kHz and the ADC has the effective resolution of 7.7 bits. The power consumption per a channel is $12\;{\mu}W$, the power supply is 3.0 V, and the core area is $2.6\;mm\;{\times}\;3.7\;mm$. The proposed analog front-end was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Journal of Advanced Marine Engineering and Technology
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• 제40권7호
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• pp.635-641
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• 2016

In order to drive a hybrid propulsion device which combines an engine and an electric propulsion unit, battery packs that contain dozens of unit cells consisting of a lithium-based battery are used to maintain the power source. Therefore, it is necessary to more strictly manage a number of battery cells at any given time. In order to manage battery cells, generally voltage, current, and temperature data under load condition are monitored from a personal computer. Other important elements required to analyze the condition of the battery are the internal resistances that are used to judge its state-of-health (SOH) and the open-circuit voltage (OCV) that is used to check the battery charging state. However, in principle, the internal resistances cannot be measured during operation because the parallel equivalent circuit is composed of internal loss resistances and capacitance. In most energy storage systems, battery management system (BMS) operations are carried out by using data such as voltage, current, and temperature. However, during operation, in the case of unexpected battery cell failure, the output voltage of the power supply can be changed and propulsion of the hybrid vehicle and vessel can be difficult. This paper covers the implementation of a high safety battery management system (HSBMS) that can estimate the OCV while the device is being driven. If a battery cell fails unexpectedly, a DC power supply with lithium iron phosphate can keep providing the load with a constant output voltage using the remainder of the batteries, and it is also possible to estimate the internal resistance.

• Proceedings of the KIPE Conference
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• 전력전자학회 2001년도 Proceedings ICPE 01 2001 International Conference on Power Electronics
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• pp.708-712
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• 2001

A new phase-shifted parallel-input/series-output (PI SO) dual inductor-fed push-pull converter for high-power step­up applications is proposed. This converter is operated at a constant duty cycle and employs an auxiliary circuit to control the output voltage with a phase-shift between the two modules. It features a voltage conversion characteristic which is linear to changes in the control input, and high step-up ratio with a greatly reduced switch turn-off stress resulting in a significant increase in the converter efficiency. It also shows a low ripple content and low root-mean-square (RMS) current in the output capacitor. The operational principle is analyzed and a comparative analysis with the conventional pulse-width-modulated (PWM) PISO dual inductor-fed push-pull converter is presented. A 50kHz, 800W, 350Vdc prototype with an input of 20-32Vdc has also been constructed to validate the proposed converter. The proposed converter compares favorably with the conventional counterpart and is considered well suited to high-power step-up applications.