• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.413-415
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• 1995

This paper presents a new approach in the design of multiple power output electronic ballasts for compact fluorescent lamps which power output range of 11W, 15W, 20W by using equivalent resistance and RLC equivalent circuit concept and frequency control. A multiple power output electronic ballast which adopts half-bridge inverter topology is set up to compare the results of PSpice simulation with experimental ones. Starting characteristics of lamp voltage, lamp current and light output are better than the existing electronic ballasts, and therefore is verified the validity of the proposed method.

• Journal of Power Electronics
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• v.19 no.3
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• pp.676-690
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• 2019

This paper presents a switched capacitor (SC) based bidirectional dc-dc converter topology for high voltage gain applications. The proposed converter is able to operate with multiple integral voltage conversion ratios based on user input. The architecture of a user-friendly, inductor-less multi-voltage-gain bidirectional dc-dc converter is proposed in this study. The inductor-less or magnetic-less design of the proposed converter makes it effective in higher temperature applications. Furthermore, the proposed converter has a reduced component count and lower voltage stress across its switches and capacitors when compared to existing SC converters. An output impedance analysis of the proposed converter is presented and compared with popular existing SC converters. The proposed converter is simulated in the OrCAD PSpice environment and the obtained results are presented. A 200 W hardware prototype of the proposed SC converter has been developed. Experimental results are presented to validate the efficacy of the proposed converter.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.235-240
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• 1998

A procedure for the optimal design of high quality rectifiers is introduced in this paper. The procedure is capable of producing different optimal designs for the same rectifier based on the objective performance required from that rectifier. A FORTRAN-based computer system designed to solve large-scale optimization problems was used in this work to obtain the optimal designs. The optimization program uses Wolfe algorithm in conjunction with a quasi-Newton algorithm as well as a projected augmented Lagrangian algorithm to solve the highly nonlinear optimization problem. The paper also introduces a detailed analysis and an application of the procedure on a boost-type zero-current switch (ZCS) single-switch three-phase rectifier introduced recently in the literature. The obtained results are compared with popular simulation packages (i. e. PSPICE and SIMCAD) to support the validity of the proposed concept.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.221-223
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• 2020

반도체 기반 고전압 펄스 발생장치에 적용 가능한 고전압 스위치는 주로 수 kV 정격의 반도체 스위치를 직렬로 스태킹하여 구성되며, 이때 각 스위치 소자에는 절연과 동기화된 각각의 게이트 신호가 인가되어야 한다. 본 논문에서는 짧은 펄스 폭의 온, 오프 게이트 펄스와, 단일 턴의 고전압 전선을 일차측으로 갖는 게이트 변압기를 통해 직렬로 구성된 반도체 스위치 스택 기반의 펄스 모듈레이터에 적용 가능한 간단한 구조의 게이트 구동회로가 설계되었다. 각 스위치에 게이트 신호를 전달하기 위해 온, 오프 게이트 펄스를 사용함으로써 게이트 변압기의 포화를 방지할 수 있으며, 이때 각 스위치의 게이트 턴-온, 오프 전압은 변압기 이차측의 제너 다이오드와 스토리지 커패시터를 통해 유지된다. Pspice 시뮬레이션을 통해 12개의 IGBT를 직렬로 구성하여 설계된 구조의 게이트 회로를 적용, 최대 10kV 펄스 출력 조건에서 안정적인 동작을 확인하고 설계를 검증하였으며 1200V 급 IGBT를 사용하여 실제 스위치 스택과 게이트 구동회로 모듈을 1리터 이내의 부피로 고밀도화하여 제작하였다.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.136-141
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• 2023

The continuous shrinking of transistors in integrated circuits leads to difficulties in improving performance, resulting in the emerging transistors such as nanosheet field-effect transistors. In this paper, we propose a TCAD-machine learning framework of nanosheet FETs to model the current-voltage characteristics. Sentaurus TCAD simulations of nanosheet FETs are performed to obtain a large amount of device data. A machine learning model of I-V characteristics is trained using the multi-layer perceptron from these TCAD data. The weights and biases obtained from multi-layer perceptron are implemented in a PSPICE netlist to verify the accuracy of I-V and the DC transfer characteristics of a CMOS inverter. It is found that the proposed machine learning model is applicable to the prediction of nanosheet field-effect transistors device and circuit performance.

• Journal of IKEEE
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• v.16 no.3
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• pp.217-223
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• 2012

This paper presents design and operational characteristics of 150 MW pulse power system for high current pulse forming network to control trigger time. The system is composed of two capacitor bank modules. Each capacitor bank module consist of a trigger vacuum switch, 9k 33kJ capacitor, an energy dump circuit, a crowbar circuit and a pulse shaping inductor and is connected in parallel. It is controlled by trigger controller to select operational module and determine triggering time. Pspice simulation was conducted about determining parameters of components such as crowbar circuit, capacitor, pulse forming inductor, trigger vacuum switch and predicting results of experiment circuit. The result of the experiment was in good agreement with the result of the simulation. The various current shapes with 300~650 us pulse width is formed by sequential firing time control of capacitor bank module. The maximum current is about 40 kA during simultaneous triggering of two capacitor bank modules. The developed 150 MW pulse power system can be applied to high current pulse power system such as rock fragmentation power sources, Rail gun, Coil gun, nano-powers, high power microwave.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.5 s.311
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• pp.36-43
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• 2006

In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.7-14
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• 2008

In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.2
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• pp.150-158
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• 2010

The operational characteristics of a resonant DC/DC converter, which can harvest thermoelectric energy, is analyzed, depending on the relative magnitudes of the input voltage and the load voltage. The resonant converter consists of LC resonant circuit connected to DC input source and a resonant pulse converter in which the input energy is transferred to the load as the resonant capacitor voltage is peak. The resonant capacitor doubles the input voltage by the resonance phenomenon. By the relative magnitude between the input voltage and the output voltage, the resonant DC/DC converter operates in three different modes. For boost mode, the peak voltage of the resonant capacitor is smaller than the load voltage. For hybrid mode, the peak voltage of the resonant capacitor is bigger than the load voltage and every switching period has both the boost mode and the direct mode. For the direct mode, the input voltage is bigger than the load voltage and the converter transfers directly the input energy to the load without the switching operation. Operation principles and the feasibility of the converter for the thermoelectric energy harvesting are verified with PSPICE simulation and experiment.