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Design of High-Speed Parallel Multiplier over Finite Field $GF(2^m)$  

Seong Hyeon-Kyeong (School of Computer, Information and Communication Engineering, Sangji University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.43, no.5, 2006 , pp. 36-43 More about this Journal
Abstract
In this paper we present a new high-speed parallel multiplier for Performing the bit-parallel multiplication of two polynomials in the finite fields $GF(2^m)$. Prior to construct the multiplier circuits, we consist of the MOD operation part to generate the result of bit-parallel multiplication with one coefficient of a multiplicative polynomial after performing the parallel multiplication of a multiplicand polynomial with a irreducible polynomial. The basic cells of MOD operation part have two AND gates and two XOR gates. Using these MOD operation parts, we can obtain the multiplication results performing the bit-parallel multiplication of two polynomials. Extending this process, we show the design of the generalized circuits for degree m and a simple example of constructing the multiplier circuit over finite fields $GF(2^4)$. Also, the presented multiplier is simulated by PSpice. The multiplier presented in this paper use the MOD operation parts with the basic cells repeatedly, and is easy to extend the multiplication of two polynomials in the finite fields with very large degree m, and is suitable to VLSI. Also, since this circuit has a low propagation delay time generated by the gates during operating process because of not use the memory elements in the inside of multiplier circuit, this multiplier circuit realizes a high-speed operation.
Keywords
Finite fields $GF(2^m)$; Parallel multiplier; Systolic multiplier; Irreducible polynomial; Reed-Solomon decoder;
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