• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.7
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• pp.56-62
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• 1998

Polysilicon resistors with high thermal stability have been fabricated by a new mixed process using POCl$_{3}$ doping and arsenic implantation. Varous temeprature coefficients, which range form 510 ppm/.deg. C to -302 ppm/.deg. C, were shown from the fabricated polysilicon resistors with sheet resistance of 58~107 .ohm./sq in the operating temeprature of 27~150.deg. C. The temperature coefficient of the polysilicon resistor by the mixed technology was about 4.3 times as low compared to the conventional polysilicon resistor using POCl$_{3}$ doped single process with the same sheet resistance of 75.ohm./sq. In addition, the mixed technology can be applied to obtain nearly zero temperature coefficient for polysilicon resistors which are reliable and insensitive to temperature.

• Electrical & Electronic Materials
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• v.7 no.3
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• pp.206-212
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• 1994

In this paper, We discuss the $POCI_3$ doping process according to the variation of deposition temperature, gas flow rate and doping time. The factors acted with $POCI_3$ doping are gas flow rate deposition temperature and time etc. Among them the temperature is the most important factor. For the $POCI_3$ flow rate, it should not exceed the resistivity saturation point developed on poly surface by annealing treatment. Therefore, this study suggests the optimum conditions of Poly-silicon treatments with the $POCI_3$ flow rate.

• Journal of the Korean Vacuum Society
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• v.19 no.5
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• pp.391-396
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• 2010

The pn junction for solar cell was prepared on p-type Si wafer by the furnace using the $POCl_3$ and oxygen mixed precursor to research the characteristic of interface at pn junction. The sheet resistance was decreased in accordance with the increasing the diffusion process time for n-type doping on p-type Si wafer. The electron affinity at the interface in the pn junction was decreased with increasing the amount of n-type doping and the sheet resistance also decreased. Consequently, the drift current due to the generation of EHP increased because of low potential barrier. The efficiency and fill factor were increased at the solar cell with increasing the diffusion process time.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.6
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• pp.43-49
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• 1997

Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

• Current Photovoltaic Research
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• v.1 no.1
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• pp.69-72
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• 2013

Combined nano- and micro-wires (CNMWs) Si arrays were prepared using PR patterning and silver-assisted electroless etching. A $POCl_3$ doping process was applied to the fabrication of CNMWs solar cells. KOH solution was used to remove bundles in CNMWs and the etching time was varied from 30 to 240 s. The lowest reflectance of 3.83% was obtained at KOH etching time of 30 s, but the highest carrier lifetime of $354{\mu}s$ was observed after the doping process at 60 s. At the same etching time, a $V_{oc}$ of 574 mV, $J_{sc}$ of $28.41mA/cm^2$, FF of 74.4%, and Eff. of 12.2% were achieved in the CNMWs solar cell. CNMWs solar cells have potential for higher efficiency by improving the post-process and surface-rear side structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1054-1056
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• 2002

High temperature Kermal diffusion from $POCl_3$ source usually used for conventional process through put of a cell manufacturing line and potentially reduce cell efficiency through bulk like time degradation. To fabricate high efficiency solar cells with minimal thermal processing, spin-on-doping(SOD) technique can be employed to emitter diffusion of a silicon solar cell. A technique is presented to emitter doping of a mono-crystalline solar cell using spin-on doping (SOD). Moreover it is shown that the sheet resistance variation with RTA temperature and time fer mono-crystalline and multi-crystalline silicon samples. This novel SOD technique was successfully used to produces 11.3% efficiency l04mm by 104mm size mono-crystalline silicon solar cells.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.28-32
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• 1992

The electrical properties of ONO interpoly dielectrics grown by polycrystalline silicon have been studied. The polysilicon layer deposited as amorphous state kept its surface smoothness even after subsequent heat cycle induced crystallization. Polysilicon was doped with a POCl$_3$ and arsenic ion implantation. Arsenic was implanted in several different doses. The effective barrier heights calculated from F-N plotting method and breakdown fields increased as the polysilicon doping concentration increased. On the other hand they mere degraded when arsenic concentration in polysilicon exceeded 2{\times}10^{20}[cm^{-3}]$. The reliability of dielectric as monitored by TDDB infant fail and breakdown field showed increasing degradation as doping concentration increased

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.413-413
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• 2016

태양전지 제작 시 에미터층을 형성하는 도핑 공정의 최적화는 캐리어 수집 확률 증가와 함께 결정질 실리콘 태양전지 고효율화를 위해 매우 중요하다. 본 연구에서는 결정질 실리콘 태양전지 다이오드의 다양한 도핑 공정으로 제작된 p-n 접합에 대한 전기적 특성 분석을 진행하였다. 도핑 공정의 경우 선 증착-후 확산 공정 시간과 가스량을 변화시켜 다양한 에미터층을 제작하였다. 선 증착 시간 변화를 주는 경우 선 증착 공정을 $825^{\circ}C$로 고정한 뒤 시간을 7분에서 17분까지 변화하고 후 확산 공정을 $845^{\circ}C$, 14분으로 고정하였다. 후 확산 시간 변화를 주는 경우는 선 증착 공정을 $825^{\circ}C$, 12분으로 고정한 뒤 후 확산 공정을 $845^{\circ}C$로 고정 하고 시간을 9분에서 19분까지 변화시켰다. 선 증착 공정을 $845^{\circ}C$ 12분, 후 확산 공정을 $845^{\circ}C$, 14분으로 고정 한 뒤 선 증착 시 POCl3양을 400 ~ 1400 SCCM까지 변화시켰고, 후 확산 시 산소량을 0 ~ 1000 SCCM까지 가변한 조건에서 에미터층에 대한 특성을 분석하였다. 결과적으로 선 증착 공정 $825^{\circ}C$ 12분, 후 확산 공정 $845^{\circ}C$ 14분에서 SCR(Space Charge Region)에서 3.81의 가장 낮은 이상 계수 값을 나타내었다. 이는 p-n접합의 내부결함이 줄어들어 태양전지의 캐리어 수명이 증가됨을 보였다. 선 증착 공정 중 $POCl_3$ 주입량 800 SCCM, 후 확산 공정 중 산소량 400 SCCM에서 $15.9{\mu}s$로 가장 높은 캐리어 수명을 나타내었다. Suns-VOC 측정 결과 $POCl_3$ 주입량 800 SCCM, 산소량 400 SCCM에서 619mV로 가장 높은 개방전압을 얻을 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.11
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• pp.1342-1349
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• 1988

The dependence of the etch rates of differently doped poly-Si films on the gas composition, the chamber pressure and the RF power was investigated in detail. The highest anisotropy and the lowest CD loss were achieved at the $SF_6$-rich compositions, i.e., $Cl_2:SF_6$=17:33 (SCCM), in the $POCl_3$-doped poly-Si. The etch rates increased for n-type dopant (phosphorus), while decreased for p-type (boron) with increasing the doping levels irrespective of plasma parameters. And from the results of the activation of doped poly-Si films the active carrier concentrations as well as the doping concentrations were found to be responsible for the increase of the etch rate of the phosphorus-doped poly-Si.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.354-357
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• 2002

Thermally grown gate oxide on 4H-SiC wafer was investigated. The oxide layers were grown at l150$^{\circ}C$ varying the carrier gas and post activation annealing conditions. Capacitance-Voltage(C-V) characteristic curves were obtained and compared using various gate electrode such as Al, Ni and poly-Si. The interface trap density can be reduced by using post oxidation annealing process in Ar atmosphere. All of the samples which were not performed a post oxidation annealing process show negative oxide effective charge. The negative oxide effective charges may come from oxygen radical. After the post oxidation annealing, the oxygen radicals fixed and the effective oxide charge become positive. The effective oxide charge is negative even in the annealed sample when we use poly silicon gate. Poly silicon layer was dope by POCl$_3$ process. The oxide layer may be affected by P ions in poly silicon layer due to the high temperature of the POCl$_3$ doping process.