• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12A
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• pp.1217-1224
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• 2008

The carrier tracking has to be basically completed for accurate positioning of Galileo satellite system. The FLL for tracking frequency errors is robust to dynamic stress causing changes of propagation time but hardly tracks accurate carrier tracking. The PLL for tracking phase errors provides accurate carrier tracking but is sensitive to dynamic stress and its tracking performance is decreased when high dynamics exist. In this paper, we design the carrier tracking loop with the FLL-assisted PLL loop filter and co-operations of FLL and PLL to achieve accurate carrier tracking in high dynamic stress. we prove the performance of designed carrier tracking loop via simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.180-185
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• 2000

In this paper, we designed 2303.15MHz Sequency synthesizer for the purpose of the phase noise prediction. For the modeling of phase noise Oersted in the designed system through inooducing the noise-modeling method suggested by Lascari we analyzied a variation of phase noise as according as that of offest frequency. Especially, for the third-order system of the PLL among some kinds of phase noise generated from VCO we analyzed the aspect of 1/f-noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically 1/f-noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor has made an ease of the access of the 1/f-noise variance. we showed a numerical formula of 1/f-noise variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.4
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• pp.653-660
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• 2001

In this paper, we designed 2303.15MHz frequency synthesizer for the purpose of the phase noise prediction. For the modeling of phase noise generated in the designed system through introducing the noise-modeling method suggested by Lascari we analyzed a variation of phase noise as according as that of offset frequency. Especially, for the third-order system of the PLL among some kinds of phase noise generated from VCO we analyzed the aspect of 1/f-noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically 1/f-noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor has made an ease of the access of the 1/f-noise variance. we showed a numerical formula of 1/f-noise variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL. As a result, In case of txco we found the reduce rapidly along the offset frequency after passed through that phase-noise was -160dBc/Hz before passed through a loop at 10kHz offset frequency and -162.6705dBc/kHz after passed through the loop, -180dBc/Hz at 100kHz offset frequency and -560dBc/kHz after passed through the loop. We can notice that the variance of third-order system more occurs (or the variance of second-order system in connection with noise bandwidth and variance factor of second-order and third-order system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.707-714
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• 2000

In this paper, using third-order system of the PLL we'll analyze the aspect of flicker noise appearing troubles in the low frequency band. Since it is difficult to analyze mathematically flicker noise in the third-order system of the PLL, introducing the concept of pseudo-damping factor using the optimized second-filter has made an ease of the access of the flicker-noise variance. we'll show a numerical formula of flicker variance in the third-order system of the PLL which is compared with that of 1/f noise variance in the second-order system of the PLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.230-235
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• 1999

In this paper, Using third-order system of the PLL we analyze the aspect of flicker noise appearing troubles In the low frequency band. Since i. Is difficult to analyze mathematically flirter noise In the third-order system of the PLL, introducing the concept of pseudo-damping factor using the optimized second-filter makes an ease of the access of the flicker-noise variance. we'll show a numerical formula of flicker variance in the third-order system of the PLL which is compared with that of 1/f-noise variance in the second-order system of the PLL.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2326-2332
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional $2^{nd}$-order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and 'on/off' depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.6
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• pp.479-486
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• 2021

In this paper, an ultra small phase locked loop (PLL) with a single capacitor loop filter has been proposed by adding a signal sensing circuit (SSC). In order to extremely reduce the size of the PLL, the passive element loop filter, which occupies the largest area, is designed with a very small single capacitor (2pF). The proposed PLL is designed to operate stably by the output of the internal negative feedback loop including the SSC acting as a negative feedback to the output of the single capacitor loop filter of the external negative feedback loop. The SSC that detects the PLL output signal change reduces the excess phase shift of the PLL output frequency by adjusting the capacitance charge of the loop filter. Although the proposed structure has a capacitor that is 1/78 smaller than that of the existing structure, the jitter size differs by about 10%. The PLL is designed using a 1.8V 180nm CMOS process and the Spice simulation results show that it works stably.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.3
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• pp.215-220
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• 2000

본 논문에서는 SRM운전에서 맥동토오크와 부하토오크의 변화로 인한 속도변경을 줄이기 위해 동적 도통각 제어 원리를 이용한 PLL(Phase Locked Loop) 속도제어 방식을 채택하였다. SRM은 많은 장점을 가지고 있으나 토오크리플에 따른 속도변동으로 정밀한 속도제어에 어려움이 있다. SRM 구동 시스템에 PLL을 적용한 결과 전동기는 강인한 정속도 운전을 할 수 있으며, 또한 운전속도에 따라 선행각을 조정함으로서 고효율 구동을 할 수 있었다. 구성된 시스템은 운전속도와 부하의 변화에 따라 선행각이 증가함으로써 뛰어난 동적 속도제어 특성을 갖고 있으며, 인버터 인가전압을 제어하는 선행각을 조정함으로서 일정부하 영역에서 높은 효율특성을 가진다. SRM 구동 시스템의 PLL 속도제어와 고효율 구동을 위한 도통각제어를 위해 TMS320F240 DSP를 사용함으로서 디지털 제어기의 유연성과 소형화를 꾀하였다.