• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.103-106
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• 2005

This paper reports design and fabrication of CMOS temperature sensor circuit using MOSIS 0.25um CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. This circuit may be applicable to the design of one-chip IC where quartz crystal resonator is directly mounted on CMOS oscillator chips.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.62-68
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• 1996

A CMOS transmitter ASIC for the ATM switching system etc., was designed to transmit 155.52 Mbps serial data transformed from 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is genrated using reference 19.44 MHz clock by an analog PLL while parallel to serial data conversion is done by a digital circuit. Circuit simulations confirm that PLL locking and data conversion are accomplished successfully. The area of the designed ASIC chip is 1.3${\times}1.0mm^2$. The locking time and the power consumption of the chip are about 600 nsec and less than 150 mW, respectively.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.11a
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• pp.208-209
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• 2005

A frequency synthesizer of 10 GHz ${\sim}$ 11 GHz for FMCW radar is designed and implemented by the form of indirect frequency synthesizer of a single loop structure. The synthesizer uses a high speed digital PLL chip. It is difficult to divide directly by using a program counter of PLL chip because the output frequency of VCO is 10 GHz ${\sim}$ 11 GHz, so we lower the frequency to 625 MHz ${\sim}$ 687.5 MHz by using a prescaler, and then divide the frequency by the program counter. The output frequency sweep of VCO from 10 GHz to 11 GHz is measured.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.249-254
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• 2005

This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2326-2332
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• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. A switch controlled loop filter is introduced into the proposed PLL instead of a conventional $2^{nd}$-order loop filter. Those three switches are controlled by the very high frequency output signal of voltage controlled oscillator. The switches are also controlled by UP/DN signals and 'on/off' depending the presence of UP/DN signals. A negative feedback functioned capacitor with a switch does make it possible to integrate the PLL into a single chip. The proposed PLL works stably even though a total of small 180pF capacitor used in the discrete loop filter. The proposed PLL has been designed with a 1.8V supply voltage, 0.18um multi - metal and multi - poly layer CMOS process and proved by Hspice simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.52-58
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• 2007

This paper describes the PLL of TCON(Timing Controller) chip for FPD(Flat Panel Display). The recent TCON requires wide range frequency operation of $8\sim135MHz$ in PLL. In order to be satisfied this requirement the new V-I converter.circuit. The V-I converter of new architecture increased the minimum/maximum current ratio which widens the operation frequency range of VCO's md also guaranteed linearity of VCO's. The proposed PLL circuits in FPD TCON show the measuring performance of loops RMS jitter in the range of $8\sim135MHz$. The designed circuit was fabricated in 1-ploy 3-metal 0.25um TSMC process technology and has a operation range or $8\sim135MHz$ with 2.5V power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.74-80
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• 2009

This paper describes a $2{\sim}6GHz$ CMOS frequency synthesizer that employs only one LC-tank voltage controlled oscillator (VCO). For wide-band operation, optimized LO signal generator is used. The LC-tank VCO oscillating in $6{\sim}8GHz$ provides the required LO frequency by dividing and mixing the VCO output clocks appropriately. The frequency synthesizer is based on a fractional-N phase locked loop (PLL) employing third-order 1-1-1 MASH type sigma-delta modulator. Implemented in a $0.18{\mu}m$ CMOS technology, the frequency synthesizer occupies the area of $0.92mm^2$ with of-chip loop filter and consumes 36mW from a 1.8V supply. The PLL is completed in less than $8{\mu}s$. The phase noise is -110dBC/Hz at 1MHz offset from the carrier.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.3
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• pp.283-289
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• 2018

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and Fvco-sampled feedforward loop filter. The proposed PLL not only reduces the chip area by replacing the resistance to a switch and a small capacitor but also reduces the variation of ${\Delta}VLPF$ and ${\Delta}{\Delta}VLPF$ to 1/6 and 1/5 respectively. The variation of ${\Delta}VLPF$ is related to the phase noise of VCO output and that of ${\Delta}{\Delta}VLPF$ is proportional to reference spurs. It has been simulated and verified with a 1.8V $0.18{\mu}m$ CMOS process and shown a good phase noise characteristics. We plan to fabricate chip based on the simulations and check performance.