• 전자공학회논문지 IE
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• v.47 no.2
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• pp.1-7
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• 2010

This paper presents a low power digital PLL architecture and design for implementation of the PLL-based frequency synthesizers. In the proposed architecture, a wide band digital logic quadricorrelator is used for preliminary frequency detector and a narrow band digital logic quadricorrelator is used for final DCO control. Also, a circuit technique for reducing leakage current is adopted in order to minimize the standby mode power consumption of the deactivated block. The proposed digital PLL is designed and verified by MyCAD with MOSIS 1.8V $0.35{\mu}m$ CMOS technology, and the simulation results show that the power consumption can be lowered by more than 20%.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.145-151
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• 2008

This paper proposes the PLL method using positive sequence voltage which is estimated by full-order state observer to find an accurate phase angle under the condition of unbalanced utility voltage. The proposed method uses the full-order state observer instead of existing method(APF All Pass Filter) to find a positive sequence of a utility voltage and this proposed method improves transient response of an estimated phase angle when a three-phase utility voltage becomes unbalanced. To compare proposed method withexisting method, experiments have been done for a phase angle detection of utility voltage when a three-phase utility voltage becomes unbalanced. Their results show that transient state response of proposed method is improved.

• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.4
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• pp.231-239
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• 2018

The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.7-8
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• 2017

The Phase-Locked Loop (PLL) is widely used in grid-tie inverter applications to achieve the synchronization between the inverter and the grid. However, its performance is deteriorated when the grid voltage is not pure sinusoidal due to the harmonics and the frequency deviation. Therefore it is important to design a high performance phase-locked loop (PLL) for the single phase inverter applications to guarantee the quality of the inverter output. In this paper a simple method to improve the performance of the PLL for the single phase inverter is proposed. The proposed PLL is able to accurately estimate the fundamental frequency component of the grid voltage even in the presence of harmonic components. In additional its transient response is fast enough to track a change in grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.5
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• pp.460-471
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• 1992

By setting a new model to describe the time-discontinuous operation of PLL loop which used tri-state and sample-hold method, the stability analysis of nonlinear PLL has been performed in z-domain and the state equations for the transient response has been introduced. Until now, the lin-ear analysis by approximation of time-discontinuous to time-continuous operation had not found then stable region of time-discontinuous digital PLL exactly. However, the analysis In z-domain by the new model has been found the unstable region where the time-continuous analysis had have not. 1'herefore the limit of loop coefficient has been computed to design digital PLL optimally.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.1
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• pp.175-181
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• 2005

This paper proposes the fuzzy-PLL control system for fast response time and precision control of automation systems. The conventional PLL has not only a jitter noise caused from such a demerit of the wide dead zone, but also a long delay interval that makes a high speed operation unable. In order to solve the problems, the proposed system, which provides the improvement in terms of the control region in high speed and precision control, first used the fuzzy control method for fast response time and when the error reaches the preset value, used the PLL method designing new PFD for precision control. The new designed multi-PFD improves the dead zone, jitter noise and response characteristics, which is consists of P-PFD(Positive edge triggered PFD) and N-PFD(Negative edge triggered PFD) and can improve response characteristics to increase PFD gain.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.445-446
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• 2014

계통 연계형 3상 인버터는 계통과 연계 운전을 위해 전력 계통과 동기화시키는 PLL 알고리즘을 사용하게 된다. 본 논문에서는 정상분 전압을 추출하는 PLL 사용을 전제로 계통 전압의 센싱 옵셋이 발생한 경우 PLL 알고리즘을 안정적으로 동작시키기 위한 PLL 보상 방법을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1872-1879
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• 1994

The design and implementation of Ku-Band frequency synthesizer was accomplished by the use of PLL and frquency multiple method. Design procedure and operation characteristics of PLL circuit were analyzed on the basis of control theory to synthesize about 1 GHz frequency which should be stable. By connecting frequency doubler and frequency eighth multiplier to the designed PLL circuit in series, Ku-Band frequency was synthesized. The validity of design method of Ku-Band frequency synthesizer was verified through experimental results.

• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.150-152
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• 2018

계통 사고 시 계통연계형 인버터에 대한 각국의 계통 규정(Grid Code)이 더욱 엄격해 지고 있다. 계통 규정은 특히, 계통 내 저전압 사고로 인한 인버터 운전계속성(Low Voltage Ride Through, LVRT)뿐만 아니라 0 전압 사고 시 운전계속성(Zero Voltage Ride Through, ZVRT)을 통해 인버터가 계통 안정화에 기여할 것을 요구하고 있다. 계통연계형 인버터는 계통전압과 인버터 출력 위상을 일치시키는 PLL제어가 적용되며 본 논문에서는 위상 추종이 어려운 0 전압 상황에서도 안정적인 위상 추종 및 인버터 출력이 가능한 PLL 방법을 제안한다. 단상 인버터에 Notch filter-PLL, APF를 이용한 dq-PLL, 및 SOGI-PLL(Second-order Generalized Intergrator)을 적용하고 독일, 미국, 및 일본의 0 전압 상황에 대해 시뮬레이션과 실험을 진행하여 제안한 PLL 기법의 ZVRT 유효성을 확인하였다.