• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3088-3090
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• 2000

In this paper, we introduce a charge pump PLL architecture which employs precharge phase frequency detector(PFD) and sequential PFD to achieve high frequency operation and fast acquisition. Operation frequency is increased by using precharge PFD when the phase difference is within -${\pi}\;{\sim}\;{\pi}$ and acquisition time is shortened by using sequential PFD and increased charge pump current when the phase difference is larger than |${\pi}$|. SO error detection range of proposed PLL structure is not limited to -${\pi}\;{\sim}\;{\pi}$. By virtue of this multi-phase frequency detector structure, the maximum operating frequency of 423MHz at 2.5V and faster acquisition were achieved by simulation.

• ETRI Journal
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• 제30권4호
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• pp.546-554
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• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.170-183
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• 2013

This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ${\Delta}{\Sigma}$ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ${\Delta}{\Sigma}$ fractional-N PLLs are discussed with simulation and hardware results. High-order ${\Delta}{\Sigma}$ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.145-151
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• 2013

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ${\mu}m$ CMOS process with a die area of 0.12 $mm^2$. The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

• 한국통신학회논문지
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• 제15권3호
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• pp.260-268
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• 1990

본 논문에서는 도약속도를 높이기 위하여 이중 주파수 합성기를 도입하였으며 시스템을 간략화하기 위하여 다음의 몇가지 방식을 제안하였다. PLL 루프에 직접 FSK 변조를 하기 위해 VCO의 이득을 선형화시켰으며, 2개의 수동상관기를 이용하여 코드동기를 얻을 수 있는 수정된 정합 필터 방식을 제안하였다.

• Journal of Electrical Engineering and Technology
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• 제7권6호
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• pp.898-904
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• 2012

This paper presents a ride-through skill of PMSG wind turbine system under the distorted and unbalanced grid voltage dips. When voltage dips occur in the grid, pitch control and generator speed control as well as a parallel resistor of DC-link help to keep the turbine's safety. Modern grid code requires a wind turbine to supply reactive currents to help voltage recovery after grid faults clearance. In order to supply reactive currents to the grid in case of the distortedly unbalanced grid voltage dips, a special PLL is needed to control the grid side converter and to regulate the grid voltages symmetrically. The proposed method is applied to 2MW multi-pole PMSG wind turbine system, and verified by simulation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.1161-1165
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• 2004

The fundamental digital control of utility-connected PV inverter are presented with detailed analysis and simulation and experimental results. PLL controller using virtual two phase detector, current controller of DC-DC converter, dc link voltage controller and inverter current controller are discussed. The novel PLL controller using virtual two phase detector can detect the information of utility voltage instantaneously and is not sensitive to the noise. Current controller of DC-DC converter, dc link voltage controller and inverter current controller are the conventional methods. We have constructed utility-Connected PV Inverter and applied to those controllers. The simulation and experimental results demonstrate an excellent performance in the single-phase grid-connected operation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2007년도 하계학술대회 논문집
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• pp.77-79
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• 2007

The phase angle of the utility voltage is used in current control of grid-tied fuel cell power converter. Therefore if the detection of phase angle is a problem, Current control is affected by the distorted phase angle. This paper presents a problem of synchronous reference frame PLL algorithm for single-phase systems and proposes compensated synchronous reference frame PLL algorithm. The proposed method helps power quality improvement of grid-tied fuel cell power converter under distorted utility conditions. Simulation and experimental results are presented to demonstrate the validity of the proposed method.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 전력전자학술대회 논문집
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• pp.506-509
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• 2001

A high power U.P.S system utilizing the parallel connection of low power U.P.S is developed. For the purpose of elimination the circular current between U.P.S.s, a digital circuit is employed. Furthermore a double phase synchronization and an interphase reactor are used to eliminate the circular current and the voltage ripples caused by the system parameter unbalances of parall connected U.P.S.s. The digital controller is implemented with ADSP21061 as aspect of a functional convenience.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1998년도 춘계종합학술대회
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• pp.258-264
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• 1998

본문에서 주파수hopping과 이동통신에서 요구되는 고속 주파수 전환이 가능한 새로운 주파수 신시사이저 (Synthesizer)를 제안한다. 종래의 PLL 주파수 신시사이저는 기준 주파수와 출력의 채널 주파수 간격이 동일하기 때문에 기준 주파수를 낮게 하면 매우 긴 동기 시간이 소요된다. 본 논문에서 제안하는 주파수 신시사이저는 새로운 제어 방법을 이용한 다단 펄스 제거 회로를 사용하여 기준 주파수와 채널 간격 주파수를 독립적으로 설정할 수 있기 때문에 종래의 신시사이저와 동일한 채널 간격의 주파수를 유지시키면서 기준 주파수를 높일 수 있고, 또한 루프(loop)이득을 크게 할 수 있다. 따라서 종래의 주파수 신시사이저보다 주파수 절환시간을 크게 단축할 수 있다. 본 논문에서는 주파수 절환시간을 1/100 정도 단축시킬 수 있음을 보여주고 있다.