• 반도체디스플레이기술학회지
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• 제14권2호
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• pp.35-40
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• 2015

This paper presents the sensorless position control of the Permanent Magnet Synchronous Motor (PMSM) using stator flux estimation and Phase Lock Loop (PLL). The field current and the torque current are required in order to perform the vector control of the PMSM. At this time, it is necessary for the torque to know the exact position of the magnetic flux generated by the permanent magnet, because the torque must be applied torque current in the direction orthogonal to the permanent magnet. In general the speed of the PMSM is controlled by using a magnetic position sensor. However, this paper, we estimates the stator flux by using the PLL method without the magnetic position sensor. This method is simple and easy, in addition it has the advantage of a stabile estimation of the rotor. Finally the proposed algorithm was confirmed by experimental results and showed the good performance.

• 전자공학회논문지S
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• 제35S권1호
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• pp.14-22
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• 1998

The Mathematic model of bit synchronization charge-pump Phase Locked Loop (PLL) is presented which takes into account the aperiodic reference pulses and the leakage current of the loop filter. We derive theoreitcal static phase error, overload and stability of bit synchronization charge-pump PLL using presented model and compare it with one of the conventional charge-pump PLL model. We can analysis bit synchronization charge-pump PLL exactly because our model takes into account the leakage current of the loop filter and aperiodic input data which are the charateristics of bit synchronization charge-pump PLL. We also verify it using HSPICE simulation with a bity synchronizer circuit.

• 전기전자학회논문지
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• 제4권2호
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• pp.266-273
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• 2000

OCXO (Oven Controlled X-tal Oscillator)의 주파수 모델이 holdover 알고리즘을 DP-PLL (Digital Processing-Phase Locked Loop) 시스템에 적용하기 위해 제안되었다. 이 모델은 온도와 OCXO의 노화에 따라 2차 다항식으로 간단하게 표현된다. 모델 변수들은 LSM (Least Squared Method)을 적용한 실험 데이터로부터 얻어진다. holdover 알고리즘은 다른 실험 데이터를 사용한 동일한 모델로 모의실험 할 수 있다.

• 한국전자파학회:학술대회논문집
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• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
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• pp.224-228
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• 2003

In this paper, for phase lock loop(PLL) synthesizer, we introduce a novel but simple and low cost frequency modulation(FM) circuit of a flat peak frequency deviation for modulation signal from high to very low frequency penetrating into the loop-bandwidth of PLL. The FM circuit was basically designed to compensate an amount of feedback of the loop filter in PLL. The circuit also includes the capability of the adjustment of peak frequency deviation and blocking the interference with the loop filter. The designed circuit was successfully implemented and showed the flat frequency deviation as expected in the design.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.200-209
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• 2008

This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.37-40
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• 2003

The 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed for applications to the miniature repeater. The miniature dual-band repeater will be used at shopping mall, basements and underground parking lots. The in-loop 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer has been developed by designing Si BJT VCO and PLL loop circuits with Colpitts. The prototype of 1.63㎓, 2.33㎓ dual-band PLL frequency synthesizer of size 19${\times}$19${\times}$8(mm) has shown operating frequencies of 1.63㎓, 2.33㎓ ranges, RF output of 1dBm(PCS), 1dBm(IMT-2000), phase noise of -100 dBc/Hz(PCS), -95dBc/Hz(IMT-2000) at 10KHz offset, harmonics suppression of -24dB c(PCS), -15dBc(IMT-2000).

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2016년도 춘계학술대회
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• pp.698-701
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• 2016

본 논문에서는 Current Modulator를 이용하여 루프 필터 커패시턴스 유효 용량을 배가 시켜 칩 크기를 줄일 수 있는 위상고정루프를 제안하였다. 제안된 위상고정루프에서는 Current Modulator로 루프 필터의 커패시턴스 유효 용량을 배가 시켜 루프 필터 커패시터 크기를 1/10로 줄였다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 기존 구조와 같은 잡음 특성과 위상고정 시간을 보여주었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.

• 대한전자공학회논문지
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• 제15권5호
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• pp.13-18
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• 1978

본 논문에서는 PLL의 pull-in 특성을 개선하기 위하여 delay switching PL난을 제시하였다. phase detector와 low grass filter사이에 간단한 RC delay회로를 삽입하고, 90° shift 시킨 Phase detector출력에 의하여 delay time을 switching하였다. 그 결과 pull-in range는 lock range의 1/2이상으로 넓힐 수 있었으며 pull-in time도 개선되었다. 이 개선된 Pull-in특성은 근사적으로 해석되었으며 실험으로 확인되었다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제52권1호
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• pp.33-38
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• 2003

This paper describes control principles of the piezoelectric ultrasonic motor which is operated by the ultrasonic vibration generated by the piezoelectric element. The piezoelectric ultrasonic motor has excellent characteristics such as compact size, noiseless motion, low speed, high torque and controllability, and has been recently applied for the practical utilization in industrial, consumer, medical and automotive fields. In this paper, the design of two-phase push-pull inverter for driving the piezoelectric ultrasonic motor is described, and a new control method of automatic resonant frequency tracking using PLL(Phase-Locked Loop) technique is mainly presented. the experimental results by this inverter system for driving the piezoelectric ultrasonic motor are illustrated herein. The inverter system with PLL technique improved the speed stability of the piezoelectric ultrasonic motor.