• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.4 s.334
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• pp.1-6
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• 2005

For the low power and low cost transceivers, direct sequence spread spec01m frequency-shift keying (DSSS-FSK) is proposed. A transmitter of the DSSS-FSK signal can be implemented by a simple direct modulation using the phase locked loop. Since the DSSS-FSK signal has negligible power around the carrier frequency, low cost direct conversion receiver can be used. Optimum coherent and semi-coherent correlation detection methods for the DSSS-FSK signal are proposed and analyzed. Segmented semi-coherent correlation detection method is proposed to improve the bit error rate performance in the large carrier frequency offset.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.63-67
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• 2009

Current mismatch in a charge pump causes degradation in spectral purity of the phase locked loops(PLLs), such as reference spurs. The current mismatch can be reduced by increasing the output resistance of the charge pump, as in a cascoded output stage. However as the supply voltage is lowered, it is hard to stack transistors. In this paper, a new method for reducing the current mismatch is proposed. The proposed method is based on a feed-forward compensation for the channel length modulation effect of the output stage. The new method has been demonstrated through simulations on typical $0.18{\mu}m$ CMOS circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.552-560
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• 2017

This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$, whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.241-247
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• 2005

This paper deals with the operation of a flywheel energy storage UPS. The UPS has good features such as long life-time, improved efficiency, no environmental problems, reduced size and space, and low maintenance cost compared with the conventional UPS using battery. The operating principle of the UPS is analysed in each mode including voltage compensation as well as uninterruptible power supply. Especially, the tracking characteristic of the disturbed phase of the source voltage after outage is analysed. The usefulness of the system is proved through simulations and experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.12B
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• pp.2141-2153
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• 2000

본 논문에서는 DMT 기반의 xDSL 시스템의 수신단에서 발생하는 샘플링 위상 옵셋과 샘플링 주파수 옵셋에 의한 타이밍 오류를 분석한 후, 디지털 수신기에서 이를 보상하기 위한 비동기식 샘플링(full digital PLL) 방식을 제안한다. 기존의 논문에서는 DMT 방식의 xDSL 시스템에서 샘플링 위상 옵셋을 delay-rotor 특성을 이용한 주파수영역 위상 회전기로 보상하는 비동기식 샘플링 방식을 제안한 바 있다. 그러나 수신단에서 샘플링 시 존재하는 타이밍 오류로 인해 저역통과 필터링된 수신신호는 더 이상 delay-rotor 특성이 성립하지 않아 성능이 크게 저하된다. 본 논문에서는 샘플링 위상 옵셋을 완벽하게 보상할 수 있는 데이터 구간의 환형 컨벌루션화(circular convolution) 방식을 제안한다. 또한 샘플링 위상 옵셋과 샘플링 주파수 옵셋이 동시에 존재하는 경우 이를 보상할 수 있는 개선된 시간/주파수 혼성영역 보상방식을 제안한다. 또한 추가의 오버헤드를 사용하지 않고 샘플링 위상 옵셋과 샘플링 주파수 옵셋을 보상할 수 있는 시간영역 보상방식을 제안한다. 마지막으로 DMT 방식의 ADSL 시스템에 본 논문에서 제안된 비동기식 샘플링 방식들을 적용하여 모의실험을 통해 성능을 분석하고 기존의 방식과 비교하여 성능의 우수성을 확인한다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.526-533
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• 2006

In this paper, we presented the synchronization module between RF shower system and RFID Reader to extend interrogating range on Mobile RFID system, Costas Loop and FPLL(Frequency/phase Lock Loop) were used. We achieved compromised range of 3MHz locking frequency, 1ms locking time and figured out remarkable Hopping frequency of the Reader. The prototype of the new designed RFID system has been tested with ISO18000-6 type-B Tag. The read range between designed RFID Reader and Tag has been measured, it increased triple times by adjusting the Shower system output level.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.469-471
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• 2008

The charge pump affects the performance of PLL. In designing the charge pump, we need to consider various issues such as current mismatch, charge sharing, feedthrough, charge injection, and leakage current. This paper propose the new charge pump circuit which is improved in terms of the current match over the existing high-speed charge pump. The simple method used for reducing current mismatch is the technique that uses a cascode in order to increase the output resistance of the charge pump. However the method limits the output voltage range of the charge pump. So the method is hard to apply as the supply voltage is lowered. Thus this paper proposes a new charge pump circuit using an op amp instead of the cascode. And the new charge pump circuit has an excellent current matching characteristics over a wide output range.

• Journal of Institute of Control, Robotics and Systems
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• v.11 no.7
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• pp.644-650
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• 2005

The expected positioning accuracies of civil users utilizing modernized GPS and Galileo are derived using the error analysis in this paper. Since, in general, the performance of DLL, PLL and FLL is proportional to chip lengths and wavelengths, the positioning accuracies from various measurements of modernized GPS and Galileo are derived as function of chip length and wavelength. These results are compared with that from GPS Ll measurement. In absolute positioning, compared to GPS C/A code only case, more than 17 times performance improvement is expected when all civil code signals of modernized GPS and Galileo (L1, L2, L5, E1, E5A and E5B) are used. In relative positioning, compared to GPS L1 carrier phase only case, more than 2 times performance improvement is expected when all civil signals of modernized GPS and Calileo are used. Furthermore, the relationship between GDOP and RGDOP in single frequency case is expanded to general case where multiple frequencies and both code and carrier phase measurements are used.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1296-1299
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• 2002

We implemented a CD signal processor operated on a CAV 48-speed CD-ROM drive into a VLSI. The CD signal processor is a mixed mode monolithic IC including servo-processor, data recovery, data-processor, and I-bit DAC. For servo signal processing, we included a DSP core, while, for CAV mode playback, we adopted a PLL with a wide recovery range. Data processor (DP) was designed to meet the yellow book specification.［2］So, the DP block consists of EFM demodulator, C1/C2 ECC block, audio processor and a block transferring data to an ATAPI chip. A modified Euclid's algorithm was used as a key equation solver for the ECC block To achieve the high-speed decoding, the RS decoder is operated by a pipelined method. Audio playability is increased by playing a CD-DA disc at the speed of 12X or 16X. For this, subcode sync and data are processed in the same way as main data processing. The overall performance of IC is verified by measuring a transfer rate from the innermost area of disc to the outermost area. At 48-speed, the operating frequency is 210 ㎒, and this chip is fabricated by 0.35 um STD90 cell library of Samsung Electronics.