[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/JSTS.2017.17.4.552

A 1.5 Gbps Transceiver Chipset in 0.13-μm CMOS for Serial Digital Interface

Lee, Kyungmin (Department of Electronic and Electrical Engineering, Ewha Womans University)
Kim, Seung-Hoon (Department of Electronic and Electrical Engineering, Ewha Womans University)
Park, Sung Min (Department of Electronic and Electrical Engineering, Ewha Womans University)

Publication Information

JSTS:Journal of Semiconductor Technology and Science / v.17, no.4, 2017 , pp. 552-560 More about this Journal

Abstract

This paper presents a transceiver chipset realized in a $0.13-{\mu}m$ CMOS technology for serial digital interface of video data transmission, which compensates the electrical cable loss of 45 dB in maximum at 1.5 Gbps. For the purpose, the TX equips pre-emphasis in the main driver by utilizing a D-FF with clocks generated from a wide-range tuning PLL. In RX, two-stage continuous-time linear equalizers and a limiting amplifier are exploited as a front-end followed by a 1/8-rate CDR to retime the data with inherent 1:8 demultiplexing function. Measured results demonstrate data recovery from 270 Mbps to 1.5 Gbps. The TX consumes 104 mW from 1.2/3.3-V supplies and occupies the area of $1.485mm^2$ , whereas the RX dissipate 133 mW from a 1.2-V supply and occupies the area of $1.44mm^2$ .

Keywords

CMOS; digital interface; equalization; pre-emphasis; receiver; serial links; transmitter;

Citations & Related Records

Reference

1	K. -D. Hwang and L. -S. Kim, "A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface", IEEE Tran. on Circ. and Sys. I, Vol. 61, No. 10, pp. 3016-3024, Oct. 2014. DOI
2	H. Higashi, et al, "5-6.4 Gbps 12 channel Transceiver with Pre-emphasis and Equalizer", Technical Digest of IEEE Symp. on VLSI Circuits, pp. 130-133, Jun. 2004.
3	S. -W. Choi, H. -B. Lee and H. -J. Park, "A Three-Data Differential Signaling Over Four Conductors With Pre-Emphasis and Equalization: A CMOS Current Mode Implementation", IEEE J. of Solid-State Circuits, Vol. 41, No. 3, pp. 633-641, Mar., 2006. DOI
4	S. Min, T. Copani, S. Kiaei and B. Bakkaloglu, "A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation", IEEE J. of Solid-State Circuits, Vol. 48, No. 5, pp. 1151-1160, May 2013. DOI
5	D. Park and S. Cho, "A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 mm CMOS", IEEE J. of Solid-State Circuits, Vol. 47, No. 12, pp. 2989-2998, Dec. 2012. DOI
6	S. Soliman, F. Yuan, K. Raahemifar, "An overview of design techniques for CMOS phase detectors", IEEE Int. Symp. on Circ. and Sys., Vol. 5 pp. 457-459, May 2002.
7	J. -S. Choi, "A 0.18um CMOS 3.5-Gb/s Continuous-time Adaptive Cable Equalizer Using Enhanced Low-Frequency Gain Method", IEEE J. of Solid-State Circuits, Vol. 39, pp. 419-425, Mar. 2004. DOI
8	W.-S. Choi et al., "A 0.45-to-0.7V 1-to-6Gb/s 0.29-to-0.58pJ/b Source-Synchronous Transceiver Using Automatic Phase Calibration in 65nm CMOS", Technical Digest of IEEE ISSCC, pp. 66-67, 2015.