• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.200-209
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• 2008

This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dual-path VCO is important for deterministic jitter (DJ) performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1667-1670
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• 2005

본 논문에서는 차세대 통신 플랫폼을 위한 PCI Express의 전송계층과 데이터 연결계층의 모든 기능을 지원하는 PCI Express 컨트롤러를 설계하였다. 설계되어진 컨트롤러는 재전송 매커니즘을 효과적으로 지원하기 위해 제안되어진 송신버퍼 구조를 가지고 있다. 이 버퍼 구조는 전송 버퍼와 재전송 버퍼를 한 개의 버퍼로 통합하여 재전송 버퍼의 공간을 유동적으로 할당할 수 있는 방법이다. 또한 설계되어진 컨트롤러의 송신단 전송계층은 제안되어진 버퍼 구조 효과적으로 지원하도록 설계되어 졌다. 설계 되어진 컨트롤러의 각 블록을 효과적으로 관리하기 위해 80C51 마이크로프로세서를 내장하여 PCI Express 프로토콜을 제공하는 프로그램을 코딩하여 포팅하였다. 또한 설계되어진 컨트롤러의 검증을 위해, Host Bridge, 로컬 마스터 디바이스, 로컬 슬레이브 디바이스를 버스 동작 모델로 구성된 테스트 벤치도 제안하였다. 또한 실제 PCI Express 프로토콜 상에서 발생할 수 있는 모든 경우를 발생 하도록 하기 위해, 각 버스 동작 모델을 위한 어셈블러 명령어들을 정의 하였다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.1
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• pp.68-75
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• 2011

The performance of peripheral devices is improving rapidly to meet the needs of users for multimedia data. Therefore, the peripheral interface with wide bandwidth and high transmission rate becomes necessary to handle large amounts of data in real time for multiple high-performance devices. PCI Express is a fast serial interface with the use of packets that are compatible with previous PCI and PCI-X. In this paper, we design and verify general peripheral interface using serial link. It includes two kinds of traffic class (TC) labels which are mapped to virtual channels (VC). The design adopts TC/VC mapping and the scheme of arbitration by priority. The design uses a packet which can be transmitted through up to four transmission lanes. The design of general peripheral interface is described in Verilog HDL and verified using ModelSim. For FPGA verification, Xilinx ISE and SPARTAN XC3S400 are used.We used Synopsys Design Compiler as a synthesis tool and the used library was MagnaChip 0.35um technology.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.5
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• pp.9-16
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• 2004

The data link layer of the PCI Express must have the transmitting buffer that contains the packets to transmit next time. Also it must have the retry buffer that contains the packets which were already transmitted but have not been acknowledged by the corresponding target device. In the separated buffer architecture, the data link layer can not transmit the packets in the transmitting buffer if the reiry buffer space is not enough. In this paper, we propose an efficient buffer architecture which merges the transmitting buffer and the retry buffer to a single buffer. Since the proposed buffer can dynamically assign the size of the transmitting buffer and the retry buffer, it can improve the buffer usage efficiency and the data transfer efficiency. The simulation result shows that the proposed buffer has the higher data transfer efficiency than the separated buffer architecture about 39% when the total buffer size is 8K byte.

• Journal of Information Processing Systems
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• v.14 no.1
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• pp.270-279
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• 2018

PCI Express (PCIe) bus, which was only used as an internal I/O bus of a computer system, has expanded its function to outside of a system, with progress of PCIe switching processor. In particular, advanced features of PCIe switching processor enable PCIe bus to serve as an interconnection network as well as connecting external devices. As PCIe switching processors more advanced, it is required to consider the different adapter card architecture. This study developed multipurpose adapter cards by applying an on-board optical module, a latest optical communications element, in order to improve transfer distance and utilization. The performance evaluation confirmed that the new adapter cards with long cable can provide the same bandwidth as that of the existing adapter cards with short copper cable.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2017.06a
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• pp.211-212
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• 2017

본 논문은 멀티채널 UHD(Ultra High Definition) 영상 녹화/재생 하드웨어 플랫폼과 서버 시스템간의 안정적인 스트림 데이터 전송을 위한 PCI Express 디바이스 드라이버 인터페이스를 제안한다. 멀티채널 기반의 하드웨어 플랫폼은 병렬 프로세스 제어가 가능하고, 서버와의 데이터 전송을 원활하게 해주는 디바이스 인터페이스가 필요하게 되는데, 본 논문에서는 PCI Express 인터페이스를 이용하여 해당 하드웨어 플랫폼을 인식하고, 쓰레드(Thread) 기반으로 멀티채널을 동작시키는 방식으로 인터페이스를 구현하였다. 본 논문에서 제안한 인터페이스는 효율적인 제어를 통해 하드웨어 플랫폼과 서버 시스템 사이의 실시간 데이터 전송을 가능하게 하였으며, 멀티채널 기반으로 안정적인 영상 콘텐츠 녹화 및 재생의 결과를 얻을 수 있었다.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.87-90
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• 2006

Nowadays, we can enjoy access to high speed network and advanced services of convergence between broadcasting and communication anywhere and anytime through a ubiquitous computing. So, now digital convergence devices come out constantly. These devices are required faster network environment for high speed data processing than before. In this paper, we describe the design of InfiniBnad network adapter, which is included two FPGA chipsets. When this adapter is installed to Digital Convergence Platform (DCP) network performance will be improved. The adapter includes 12channel serial ports for external communication and internally, uses PCI-Express bus. We have finished the test of high speed serial based network adapter through composing complete InfiniBand network and applied fabric management software. So, we have verified that it can be applied on DCP environment.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.39-49
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• 2006

This paper proposes an efficient verification environment of PCI Express controller that is the future I/O interface. This verification environment consists of a test vector generator, a test bench, and two abstract memories. We also define the assembler set to generate the verification scenarios. In this paper, we propose the random test environment which consists of a random vector generator, a .simulator part, and a compare engine. This verification methodology is useful to find the special errors which are not detected by the basic-behavioral test and hardware-design test.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.543-544
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• 2006

This paper describes a simple real-time monitoring system for use in measurement subsystem of contact wire and geometry of overhead contact wire in electric railway. The system has been consists of a high speed CMOS camera with resolution $1024\;{\times}\;1280$ pixels, line type laser source with a power equal to 300 mW, and PC-based image acquisition system with PCI Express slot. National instrument LabVIEW (8.0) and vision acquisition software have been used in application programming interface for image acquisition, display, and storage with a frequency of sampling of 500 acquisitions per second.

• Journal of Korea Society of Industrial Information Systems
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• v.23 no.4
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• pp.23-31
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• 2018

This paper presented the implementation and design of the 2T-2R wireless HD video streaming systems over 1.7 GHz frequency band using 3GPP LTE-TDD standard on NI USRP RIO SDR platform. The baseband of the system used USRP RIO that are stored in Xilinx Kintex-7 chip to implement LTE-TDD transceiver modem, the signal that are transmitted from USRP RIO up or down converts to 1.7 GHz by using self-designed 1.7 GHz RF transceiver modules and it is finally communicated HD video data through self-designed 2x9 sub array antennas. It is that communication method between USRP RIO and Host PC use PCI express x4 to minimize delay of data to transmit and receive. The implemented system show high error vector magnitude performance above 32 dBc and to transmit and receive HD video in experiment environment anywhere. The proposed hybrid beam forming system could be used not only in the future 5G mobile communication systems under 6 GHz frequency band but also in the systems over 6 GHz frequency band like ones in mmWave frequency bands.